公开(公告)号：US20190067012A1

公开(公告)日：2019-02-28

申请号：US15692221

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An LIN ,  Chun-Hsiung LIN ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Cheng-Yu YANG ,  Yen-Ting CHEN

IPC: H01L21/285 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.

公开(公告)号：US20190148519A1

公开(公告)日：2019-05-16

申请号：US15875485

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan LEE ,  Bo-Yu LAI ,  Chi-On CHUI ,  Cheng-Yu YANG ,  Yen-Ting CHEN ,  Sai-Hooi YEONG ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/306 ,  H01L21/762

Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

公开(公告)号：US20160240536A1

公开(公告)日：2016-08-18

申请号：US14621814

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Kai-Hsuan LEE ,  Cheng-Yu YANG ,  Hsiang-Ku SHEN ,  Han-Ting TSAI ,  Yimin HUANG

IPC: H01L27/092 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/207 ,  H01L29/36

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/161 ,  H01L29/267 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate. The semiconductor device structure also includes a first doped structure over the semiconductor substrate and adjacent to the first gate stack. The first doped structure includes a III-V compound semiconductor material and a dopant. The semiconductor device structure further includes a second doped structure over the semiconductor substrate and adjacent to the second gate stack. The second doped structure includes the III-V compound semiconductor material and the dopant. One of the first doped structure and the second doped structure is an n-type semiconductor structure, and the other one of the first doped structure and the second doped structure is a p-type semiconductor structure.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底和半导体衬底上的第一栅极堆叠和第二栅极堆叠。 半导体器件结构还包括在半导体衬底上并与第一栅极叠层相邻的第一掺杂结构。 第一掺杂结构包括III-V族化合物半导体材料和掺杂剂。 半导体器件结构还包括在半导体衬底上并与第二栅极堆叠相邻的第二掺杂结构。 第二掺杂结构包括III-V族化合物半导体材料和掺杂剂。 第一掺杂结构和第二掺杂结构之一是n型半导体结构，第一掺杂结构和第二掺杂结构中的另一个是p型半导体结构。

公开(公告)号：US20210035806A1

公开(公告)日：2021-02-04

申请号：US17074110

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

公开(公告)号：US20170352762A1

公开(公告)日：2017-12-07

申请号：US15226321

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu YANG ,  Kai-Hsuan LEE ,  Sheng-Chen WANG ,  Sai-Hooi YEONG ,  Yi-Fang PAI ,  Yen-Ming CHEN

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/31111 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.

公开(公告)号：US20160240651A1

公开(公告)日：2016-08-18

申请号：US14622180

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kai-Hsuan LEE ,  Cheng-Yu YANG ,  Hsiang-Ku SHEN ,  Han-Ting TSAI ,  Yimin HUANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L21/0223 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/495 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/802

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack over a portion of the fin structure, and the fin structure includes an intermediate portion under the gate stack and upper portions besides the intermediate portion. The semiconductor device structure further includes a contact layer over the fin structure. The contact layer includes a metal material, and the upper portions of the fin structure also include the metal material.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的半导体衬底和鳍状结构。 半导体器件结构还包括在鳍结构的一部分上的栅极堆叠，并且鳍结构包括在栅叠层下方的中间部分和除了中间部分之外的上部。 半导体器件结构还包括在鳍结构上的接触层。 接触层包括金属材料，翅片结构的上部还包括金属材料。

公开(公告)号：US20170207095A1

公开(公告)日：2017-07-20

申请号：US14996031

申请日：2016-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.