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    CAPPING LAYER FOR GATE ELECTRODES
    1.
    发明申请
    CAPPING LAYER FOR GATE ELECTRODES 有权

    公开(公告)号：US20210384322A1

    公开(公告)日：2021-12-09

    申请号：US17408985

    申请日：2021-08-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Hsiang LIN ,  Teng-Chun TSAI ,  Huang-Lin CHAO ,  Akira MINEJI

    IPC: H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L21/311 ,  H01L21/321 ,  H01L29/78

    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

    FIN ISOLATION STRUCTURE FOR FINFET AND METHOD OF FORMING THE SAME
    3.
    发明申请
    FIN ISOLATION STRUCTURE FOR FINFET AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20200091007A1

    公开(公告)日：2020-03-19

    申请号：US16277326

    申请日：2019-02-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chu-An LEE ,  Chen-Hao WU ,  Peng-Chung JANGJIAN ,  Chun-Wen HSIAO ,  Teng-Chun TSAI ,  Huang-Lin CHAO

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

    SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURES
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURES 有权

    公开(公告)号：US20210265220A1

    公开(公告)日：2021-08-26

    申请号：US17006161

    申请日：2020-08-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pei-Wei LEE ,  Pang-Yen TSAI ,  Tsungyu HUNG ,  Huang-Lin CHAO

    IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

    Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.

    CAPPING LAYER FOR GATE ELECTRODES
    8.
    发明申请
    CAPPING LAYER FOR GATE ELECTRODES 有权

    公开(公告)号：US20210057543A1

    公开(公告)日：2021-02-25

    申请号：US16548918

    申请日：2019-08-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chin-Hsiang LIN ,  Teng-Chun TSAI ,  Akira MINEJI ,  Huang-Lin CHAO

    IPC: H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L21/311 ,  H01L21/321

    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer haying a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

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