公开(公告)号：US20250140563A1

公开(公告)日：2025-05-01

申请号：US19004041

申请日：2024-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L21/306 ,  G06N20/00 ,  H01L21/283 ,  H10D62/10 ,  H10D64/27 ,  H10D84/83

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process. The process system then uses the selected process conditions data for the next etching process.

公开(公告)号：US20240376605A1

公开(公告)日：2024-11-14

申请号：US18782667

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: C23C16/52 ,  C23C16/455 ,  C23C16/458 ,  G05B13/04 ,  H01L21/02

Abstract: A thin-film deposition system deposits thin films on semiconductor wafers. The thin-film deposition system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for a next deposition process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted thin-film data that matches the target thin-film data. The deposition system then uses the static and dynamic process conditions data for the next thin-film deposition process.

公开(公告)号：US20230253309A1

公开(公告)日：2023-08-10

申请号：US18133970

申请日：2023-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Shih Wei BIH ,  Yen-Yu CHEN

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L23/5226 ,  H01L21/3105 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/02164 ,  H01L21/76843

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

公开(公告)号：US20230057278A1

公开(公告)日：2023-02-23

申请号：US17406879

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Chung-Liang CHENG ,  I-Ming CHANG ,  Yao-Sheng HUANG ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/3115

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

公开(公告)号：US20230040346A1

公开(公告)日：2023-02-09

申请号：US17701402

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Huang-Lin CHAO ,  Chung-Liang CHENG ,  Pinyen LIN ,  Chun-Chun LIN ,  Tzu-Li LEE ,  Yu-Chia LIANG ,  Duen-Huei HOU ,  Wen-Chung LIU ,  Chun-I WU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

公开(公告)号：US20220359698A1

公开(公告)日：2022-11-10

申请号：US17870554

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Peng-Soon Lim ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28

Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

公开(公告)号：US20220077296A1

公开(公告)日：2022-03-10

申请号：US17532062

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Ziwei FANG ,  Chun-I WU ,  Huang-Lin CHAO

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US20220013523A1

公开(公告)日：2022-01-13

申请号：US17196221

申请日：2021-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/94 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

公开(公告)号：US20210193828A1

公开(公告)日：2021-06-24

申请号：US16718862

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.

公开(公告)号：US20210184008A1

公开(公告)日：2021-06-17

申请号：US17190236

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.