公开(公告)号：US20200373400A1

公开(公告)日：2020-11-26

申请号：US16690645

申请日：2019-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Ziwei Fang ,  Chun-I WU ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US20240088227A1

公开(公告)日：2024-03-14

申请号：US18516215

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Chun-I WU ,  Huang-Lin CHAO

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

公开(公告)号：US20200152746A1

公开(公告)日：2020-05-14

申请号：US16277262

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Wen TSAU ,  Chun-I WU ,  Ziwei FANG ,  Huang-Lin CHAO ,  I-Ming CHANG ,  Chung-Liang CHENG ,  Chih-Cheng LIN

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

公开(公告)号：US20230040346A1

公开(公告)日：2023-02-09

申请号：US17701402

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Huang-Lin CHAO ,  Chung-Liang CHENG ,  Pinyen LIN ,  Chun-Chun LIN ,  Tzu-Li LEE ,  Yu-Chia LIANG ,  Duen-Huei HOU ,  Wen-Chung LIU ,  Chun-I WU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

公开(公告)号：US20220077296A1

公开(公告)日：2022-03-10

申请号：US17532062

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Ziwei FANG ,  Chun-I WU ,  Huang-Lin CHAO

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.