公开(公告)号：US20210351278A1

公开(公告)日：2021-11-11

申请号：US17228415

申请日：2021-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.

公开(公告)号：US20210280679A1

公开(公告)日：2021-09-09

申请号：US17327584

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Peng-Soon LIM ,  Zi-Wei FANG

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill metal over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.

公开(公告)号：US20210020786A1

公开(公告)日：2021-01-21

申请号：US16515898

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer,

公开(公告)号：US20220216318A1

公开(公告)日：2022-07-07

申请号：US17700424

申请日：2022-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Peng-Soon LIM ,  Zi-Wei FANG ,  Cheng-Ming LIN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/28 ,  H01L29/10

Abstract: A method includes forming a semiconductor fin; forming a gate dielectric layer over the semiconductor fin; depositing a first work function metal layer over the gate dielectric layer, the first work function metal layer having a first concentration of a work function material; depositing a second work function metal layer over the first work function metal layer, the second work function metal layer having a second concentration of the work function material, wherein the first concentration is higher than the second concentration; and forming a gate electrode over the second work function metal layer.

公开(公告)号：US20190165116A1

公开(公告)日：2019-05-30

申请号：US16031859

申请日：2018-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Peng-Soon LIM ,  Zi-Wei FANG ,  Cheng-Ming LIN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer.

公开(公告)号：US20180161828A1

公开(公告)日：2018-06-14

申请号：US15490075

申请日：2017-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-An YANG ,  Hao-Ming CHANG ,  Shao-Chi WEI ,  Kuo-Chin LIN ,  Sheng-Chang HSU ,  Li-Chih LU ,  Cheng-Ming LIN

IPC: B08B3/08 ,  H01L21/02 ,  H01L21/027 ,  H01L21/66 ,  H01L21/67 ,  B08B3/10 ,  H04N5/33 ,  G01J5/10 ,  G01J5/00

CPC classification number: G01J5/0037 ,  G01J5/10 ,  G01J2005/0077 ,  G01J2005/0081 ,  G03F7/3021 ,  H01L21/02052 ,  H01L21/67051 ,  H01L21/67253 ,  H01L21/67288

Abstract: A method for processing a substrate is provided. The method includes supplying a first flow of a chemical solution into a processing chamber, configured to process the substrate, via a first dispensing nozzle. The method further includes producing a first thermal image of the first flow of the chemical solution. The method also includes performing an image analysis on the first thermal image. In addition, the method includes moving the substrate into the processing chamber when the result of the analysis of the first thermal image is within the allowable deviation from the baseline.

公开(公告)号：US20240186414A1

公开(公告)日：2024-06-06

申请号：US18402455

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20200279929A1

公开(公告)日：2020-09-03

申请号：US16875877

申请日：2020-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Peng-Soon LIM ,  Zi-Wei FANG

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions, and a gate stack. The pair of source/drain regions is on the semiconductor substrate. The gate stack is laterally between the source/drain regions and includes a gate dielectric layer over the semiconductor fin, a metal element-containing layer over the gate dielectric layer, and a fill metal layer over the metal element-containing layer. The metal element-containing layer has a dopant, and a concentration of the dopant in an upper portion of the metal element-containing layer is higher than a concentration of the dopant in a bottom portion of the metal element-containing layer.

公开(公告)号：US20190165113A1

公开(公告)日：2019-05-30

申请号：US16059900

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Peng-Soon LIM ,  Zi-Wei FANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.

公开(公告)号：US20190146326A1

公开(公告)日：2019-05-16

申请号：US15905543

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh TIEN ,  Cheng-Hsuen CHIANG ,  Chih-Ming CHEN ,  Cheng-Ming LIN ,  Yen-Wei HUANG ,  Hao-Ming CHANG ,  Kuo Chin LIN ,  Kuan-Shien LEE

IPC: G03F1/32

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.