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公开(公告)号:US20200335608A1
公开(公告)日:2020-10-22
申请号:US16920197
申请日:2020-07-02
发明人: Yao-Sheng HUANG , Hung-Chang SUN , I-Ming CHANG , Zi-Wei FANG
IPC分类号: H01L29/66 , H01L21/02 , H01L29/78 , H01L29/08 , H01L21/311
摘要: A semiconductor includes a substrate, a semiconductor fin, an STI structure, a fin sidewall spacer, and a doped silicon layer. The semiconductor fin extends from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The fin sidewall spacer extends along a middle portion of the semiconductor fin that is above the lower portion of the semiconductor fin. The doped silicon layer wraps around three sides of an upper portion of the semiconductor fin that is above the middle portion of the semiconductor fin.
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公开(公告)号:US20240234212A1
公开(公告)日:2024-07-11
申请号:US18416737
申请日:2024-01-18
发明人: Peng-Soon LIM , Zi-Wei FANG
IPC分类号: H01L21/8234 , H01L27/088 , H01L21/285 , H01L29/66
CPC分类号: H01L21/82345 , H01L21/823431 , H01L21/823456 , H01L27/0886 , H01L21/28562 , H01L21/28568 , H01L29/66545
摘要: A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.
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公开(公告)号:US20200294851A1
公开(公告)日:2020-09-17
申请号:US16888929
申请日:2020-06-01
发明人: Hung-Chang SUN , Po-Chin CHANG , Akira MINEJI , Zi-Wei FANG , Pinyen LIN
IPC分类号: H01L21/768 , H01L27/088 , H01L21/8234 , H01L23/535 , H01L23/532
摘要: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.
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公开(公告)号:US20230327004A1
公开(公告)日:2023-10-12
申请号:US18326682
申请日:2023-05-31
发明人: Yao-Sheng HUANG , Hung-Chang SUN , I-Ming CHANG , Zi-Wei FANG
IPC分类号: H01L29/66 , H01L21/02 , H01L29/78 , H01L29/08 , H01L21/311
CPC分类号: H01L29/66795 , H01L21/02661 , H01L21/02513 , H01L21/02488 , H01L21/02639 , H01L21/02532 , H01L21/0262 , H01L21/02675 , H01L21/02592 , H01L21/02598 , H01L29/66545 , H01L29/785 , H01L29/0847 , H01L21/31116 , H01L21/30604
摘要: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.
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公开(公告)号:US20210296507A1
公开(公告)日:2021-09-23
申请号:US17338426
申请日:2021-06-03
发明人: Chih-Yu CHANG , Hsiang-Pi CHANG , Zi-Wei FANG
IPC分类号: H01L29/786 , H01L21/28 , H01L21/265 , H01L21/324 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/49
摘要: A method includes following steps. A silicon germanium layer is formed on a substrate. A surface layer of the silicon germanium layer is oxidized to form an interfacial layer comprising silicon oxide and germanium oxide. The interfacial layer is nitridated. A metal gate structure is formed over the nitridated interfacial layer.
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公开(公告)号:US20200279929A1
公开(公告)日:2020-09-03
申请号:US16875877
申请日:2020-05-15
发明人: Cheng-Ming LIN , Peng-Soon LIM , Zi-Wei FANG
IPC分类号: H01L29/417 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78
摘要: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions, and a gate stack. The pair of source/drain regions is on the semiconductor substrate. The gate stack is laterally between the source/drain regions and includes a gate dielectric layer over the semiconductor fin, a metal element-containing layer over the gate dielectric layer, and a fill metal layer over the metal element-containing layer. The metal element-containing layer has a dopant, and a concentration of the dopant in an upper portion of the metal element-containing layer is higher than a concentration of the dopant in a bottom portion of the metal element-containing layer.
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公开(公告)号:US20200035811A1
公开(公告)日:2020-01-30
申请号:US16191244
申请日:2018-11-14
发明人: Yao-Sheng HUANG , Hung-Chang SUN , I-Ming CHANG , Zi-Wei FANG
IPC分类号: H01L29/66 , H01L21/311 , H01L21/02 , H01L29/78 , H01L29/08
摘要: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.
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公开(公告)号:US20190165185A1
公开(公告)日:2019-05-30
申请号:US15919070
申请日:2018-03-12
发明人: Chih-Yu CHANG , Hsiang-Pi CHANG , Zi-Wei FANG
IPC分类号: H01L29/786 , H01L21/28 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/66
摘要: A method includes forming a channel region on a semiconductor substrate. An interfacial layer is formed on the channel region. The interfacial layer is treated with trimethyl aluminum (TMA). A high-k dielectric layer is formed on the interfacial layer after treating the interfacial layer with TMA. A gate electrode is formed on the high-k dielectric layer. The treating the interfacial layer with TMA and forming the high-k dielectric layer are performed in the same chamber. The interfacial layer is annealed before treating the interfacial layer with TMA. The annealing the interfacial layer and treating the interfacial layer with TMA are performed in different chambers.
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公开(公告)号:US20190165113A1
公开(公告)日:2019-05-30
申请号:US16059900
申请日:2018-08-09
发明人: Cheng-Ming LIN , Peng-Soon LIM , Zi-Wei FANG
IPC分类号: H01L29/417 , H01L29/66 , H01L29/78 , H01L21/8234
摘要: A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.
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公开(公告)号:US20230282753A1
公开(公告)日:2023-09-07
申请号:US18316550
申请日:2023-05-12
发明人: Chih-Yu CHANG , Hsiang-Pi CHANG , Zi-Wei FANG
IPC分类号: H01L29/786 , H01L21/28 , H01L21/265 , H01L21/324 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/49
CPC分类号: H01L29/78696 , H01L21/28185 , H01L21/26513 , H01L21/28088 , H01L21/28238 , H01L21/324 , H01L29/66636 , H01L29/0673 , H01L29/0847 , H01L29/1054 , H01L29/42392 , H01L29/4966 , H01L29/66545 , H01L29/0653 , H01L29/42364 , H01L21/28202
摘要: A semiconductor device includes a silicon germanium channel, a germanium-free interfacial layer, a high-k dielectric layer, and a metal gate electrode. The silicon germanium channel is over a substrate. The germanium-free interfacial layer is over the silicon germanium channel. The germanium-free interfacial layer is nitridated. The high-k dielectric layer is over the germanium-free interfacial layer. The metal gate electrode is over the high-k dielectric layer.
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