公开(公告)号：US20180096898A1

公开(公告)日：2018-04-05

申请号：US15282981

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Chia-Ping LO ,  Liang-Gi YAO ,  Weng CHANG ,  Yee-Chia YEO ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

公开(公告)号：US20210376138A1

公开(公告)日：2021-12-02

申请号：US16887203

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Ji-Cheng CHEN ,  Weng CHANG ,  Chi On CHUI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

公开(公告)号：US20160336420A1

公开(公告)日：2016-11-17

申请号：US14714221

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yuan CHOU ,  Chung-Chiang WU ,  Da-Yuan LEE ,  Weng CHANG

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L29/495 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28562 ,  H01L21/76877 ,  H01L21/76879 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.

Abstract translation: 制造Fin FET的方法包括形成包括上层的鳍结构。 上层的一部分从隔离绝缘层暴露出来。 在鳍部结构的一部分上形成虚拟栅极结构。 虚拟栅极结构包括伪栅极电极层和伪栅极电介质层。 在虚拟栅极结构上形成层间绝缘层。 去除虚拟栅极结构从而形成空间。 在该空间中形成栅介质层。 在空间中的栅电介质上形成第一金属层。 第二金属层形成在空间中的第一金属层之上。 第一和第二金属层被部分去除，从而减小第一和第二金属层的高度。 在部分去除的第一和第二金属层上形成第三金属层。

公开(公告)号：US20180308765A1

公开(公告)日：2018-10-25

申请号：US16016862

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Chia Ping LO ,  Liang-Gi YAO ,  Weng CHANG ,  Yee-Chia YEO ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.

公开(公告)号：US20190304846A1

公开(公告)日：2019-10-03

申请号：US15937472

申请日：2018-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Yu LEE ,  Huicheng CHANG ,  Che-Hao CHANG ,  Ching-Hwanq SU ,  Weng CHANG ,  Xiong-Fei YU

IPC: H01L21/8238 ,  H01L27/092

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

公开(公告)号：US20180261459A1

公开(公告)日：2018-09-13

申请号：US15979938

申请日：2018-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen TSAI ,  Hsin-Yi LEE ,  Chung-Chiang WU ,  Da-Yuan LEE ,  Weng CHANG ,  Ming-Hsing TSAI

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  C23C14/58 ,  C23C16/56 ,  C23C16/455

CPC classification number: H01L21/28105 ,  C23C14/58 ,  C23C14/5846 ,  C23C14/5873 ,  C23C16/02 ,  C23C16/06 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/56 ,  H01L21/02697 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76838 ,  H01L21/76886 ,  H01L29/4966 ,  H01L29/66795

Abstract: A system for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

公开(公告)号：US20230015761A1

公开(公告)日：2023-01-19

申请号：US17875561

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Ji-Cheng CHEN ,  Weng CHANG ,  Chi On CHUI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

公开(公告)号：US20200083112A1

公开(公告)日：2020-03-12

申请号：US16687152

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Chia Ping LO ,  Liang-Gi YAO ,  Weng CHANG ,  Yee-Chia YEO ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L21/268 ,  H01L21/02 ,  H01L21/8234

Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.

公开(公告)号：US20170110324A1

公开(公告)日：2017-04-20

申请号：US15192570

申请日：2016-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen TSAI ,  Hsin-Yi LEE ,  Chung-Chiang WU ,  Da-Yuan LEE ,  Weng CHANG ,  Ming-Hsing TSAI

IPC: H01L21/28 ,  C23C16/455

CPC classification number: H01L21/28105 ,  C23C14/58 ,  C23C14/5846 ,  C23C14/5873 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/02697 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76838 ,  H01L21/76886

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.