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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150279991A1

    公开(公告)日：2015-10-01

    申请号：US14721004

    申请日：2015-05-26

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Myung-Geun SONG

    IPC分类号： H01L29/78 ,  H01L29/417

    CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

    摘要： Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

    摘要翻译： 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

    METHODS OF FORMING GATES OF SEMICONDUCTOR DEVICES
    3.
    发明申请
    METHODS OF FORMING GATES OF SEMICONDUCTOR DEVICES 有权
    形成半导体器件栅的方法

    公开(公告)号：US20140235047A1

    公开(公告)日：2014-08-21

    申请号：US14264622

    申请日：2014-04-29

    申请人： Samsung Electronics Co., Ltd.

    发明人： JONG-WON LEE ,  Bo-Un YOON ,  Seung-Jae LEE

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28008 ,  H01L21/28105 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545

    摘要： Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

    摘要翻译： 提供了形成半导体器件的栅极的方法。 所述方法可以包括在具有第一导电类型的第一衬底区域中形成第一凹槽，并在具有第二导电类型的第二衬底区域中形成第二凹部。 所述方法还可以包括在第一和第二凹部中形成高k层。 所述方法还可以包括在第一和第二衬底区域中的高k层上提供第一金属，第一金属设置在第二凹槽内。 所述方法还可以包括从第二凹部移除第一金属的至少一部分，同时保护第一凹槽内的材料不被去除。 所述方法还可以包括在从第二凹部去除第一金属的至少一部分之后，在第二凹部内提供第二金属。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20140080296A1

    公开(公告)日：2014-03-20

    申请号：US13944087

    申请日：2013-07-17

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jae-Jik BAEK ,  Ji-Hoon CHA ,  Bo-Un YOON ,  Kwang-Wook LEE ,  Jeong-Nam HAN

    IPC分类号： H01L21/306

    CPC分类号： H01L21/30604 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成栅极图案，并且使用第一湿蚀刻工艺蚀刻栅极图案的侧面以形成第一凹部。 第一湿蚀刻工艺包括使用含有包含羟基官能团（-OH）的第一化学物质和能够氧化底物的第二化学物质的蚀刻剂。 第二化学物质的浓度为第一化学物质浓度的1.5倍以下。

    METHODS FOR FABRICATING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHODS FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20170040436A1

    公开(公告)日：2017-02-09

    申请号：US15191555

    申请日：2016-06-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seung-Jae LEE ,  Ja-Eung KOO ,  Ho-Young KIM ,  Yeong-Bong PARK ,  Il-Su PARK ,  Bo-Un YOON ,  Il-Young YOON ,  Youn-Su HA

    IPC分类号： H01L29/66 ,  H01L21/321 ,  H01L29/417 ,  H01L21/28

    CPC分类号： H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

    摘要： A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

    摘要翻译： 一种用于制造半导体器件的方法可以包括在衬底的第一区域中形成具有第一阈值电压的第一晶体管，在衬底的第二区域中形成具有小于第一阈值电压的第二阈值电压的第二晶体管，形成 在第三区域中的第三层间绝缘膜，并且平坦化第一晶体管，第二晶体管和第三层间绝缘膜。 第一晶体管可以包括具有第一高度的第一栅极电极和具有第一高度的第一层间绝缘膜，并且第二晶体管可以包括具有比第一高度短的第二高度的第二栅极电极和第二层间绝缘膜， 第二高度。 第三层间绝缘膜可以具有第一高度。

    METHOD OF FORMING A PLUG, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME, POLISHING CHAMBER USED FOR MANUFACTURING THE SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHOD OF FORMING A PLUG, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME, POLISHING CHAMBER USED FOR MANUFACTURING THE SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE 审中-公开
    形成插片的方法，制造使用其的半导体器件的方法，用于制造半导体器件的抛光室和半导体器件

    公开(公告)号：US20170040208A1

    公开(公告)日：2017-02-09

    申请号：US15142043

    申请日：2016-04-29

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seung-Hoon CHOI ,  Ho-Young KIM ,  Gi-Gwan PARK ,  Hyun-Kyung BAE ,  Bo-Un YOON ,  Il-Young YOON

    IPC分类号： H01L21/768

    CPC分类号： H01L21/7684 ,  B24B37/042 ,  H01L21/67219 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/41791

    摘要： A method of forming a plug and manufacturing a semiconductor device, a polishing chamber, and a semiconductor device, the method of forming a plug including forming an opening in an insulating interlayer pattern on a substrate; forming a metal layer to fill the opening; performing a first CMP process during a first time period until a top surface of the insulating interlayer pattern is exposed while pressing the substrate onto a first polishing pad to polish the metal layer; performing a second CMP process during a second time period while pressing the substrate onto a second polishing pad to polish the metal layer and the insulating interlayer pattern, so that a metal plug is formed in the insulating interlayer pattern; and performing a first cleaning process on the second polishing pad while keeping the substrate spaced apart from the second polishing pad on the second platen.

    摘要翻译： 一种形成插头并制造半导体器件，抛光室和半导体器件的方法，包括在衬底上形成绝缘层间图案中的开口的形成插头的方法; 形成金属层以填充开口; 在第一时间段内执行第一CMP处理直到绝缘层间图案的顶表面暴露，同时将基板压在第一抛光垫上以抛光金属层; 在第二时间段内执行第二CMP处理，同时将衬底按压到第二抛光垫上以抛光金属层和绝缘层间图案，从而在绝缘层间图案中形成金属插塞; 以及在所述第二台板上保持与所述第二抛光垫间隔开的所述基板的同时对所述第二抛光垫进行第一清洁处理。

    Methods of Fabricating Semiconductor Devices
    9.
    发明申请
    Methods of Fabricating Semiconductor Devices 有权
    制造半导体器件的方法

    公开(公告)号：US20160104788A1

    公开(公告)日：2016-04-14

    申请号：US14815225

    申请日：2015-07-31

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yeon-Tack RYU ,  Ho-Young KIM ,  Myoung-Hwan OH ,  Bo-Un YOON ,  Jun-Hwan YIM

    IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/283

    CPC分类号： H01L29/66545 ,  H01L21/31053 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    摘要： Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask.

    摘要翻译： 提供了制造半导体器件的半导体器件和方法。 所述方法可以包括在基底上形成层间绝缘层。 层间绝缘层可以包围虚拟硅栅极并且可以暴露虚拟硅栅极的顶表面。 所述方法还可以包括使所述层间绝缘层的一部分凹陷，使得所述虚拟硅栅极的一部分突出于所述凹陷层间绝缘层的顶表面之上，并在所述凹陷层间绝缘层上形成蚀刻停止层。 蚀刻停止层的顶表面可以与虚拟硅栅极的顶表面共面定位。 所述方法还可以包括通过使用蚀刻停止层作为掩模去除伪硅栅极来形成暴露衬底的沟槽。