公开(公告)号：US20150279991A1

公开(公告)日：2015-10-01

申请号：US14721004

申请日：2015-05-26

申请人： Samsung Electronics Co., Ltd.

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Myung-Geun SONG

IPC分类号： H01L29/78 ,  H01L29/417

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

摘要： Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

摘要翻译： 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

公开(公告)号：US20150050793A1

公开(公告)日：2015-02-19

申请号：US14286108

申请日：2014-05-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Young-Sang YOUN ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Byung-Kwon CHO ,  Ji-Hoon CHA

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L2221/1063

摘要： A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

摘要翻译： 一种用于形成沟槽的方法包括蚀刻氧化物层以在其中形成沟槽，沿着沟槽的表面共形形成第一反应层，第一反应层包括沟槽上部的第一区域和第二区域 沟槽的下部，通过使第一量的蚀刻气体与第一反应层的第一区域反应形成阻挡层，并且通过使第二量的蚀刻气体反应来蚀刻第二区域的下部的氧化物层 与第一反应层的第二区域相比，第二量的蚀刻气体大于第一量的蚀刻气体。

公开(公告)号：US20190096712A1

公开(公告)日：2019-03-28

申请号：US15978303

申请日：2018-05-14

申请人： Samsung Electronics Co., Ltd.

发明人： Sang-Jine PARK ,  Byung-Kwon CHO ,  Yong-Jhin CHO ,  Yong-Sun KO ,  Yeon-Jin GIL ,  Kwang-Wook LEE

IPC分类号： H01L21/67 ,  H01L21/302 ,  H01L21/66

CPC分类号： H01L21/67092 ,  H01L21/302 ,  H01L21/6719 ,  H01L21/67253 ,  H01L22/12

摘要： Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.

公开(公告)号：US20160359017A1

公开(公告)日：2016-12-08

申请号：US15239200

申请日：2016-08-17

申请人： Samsung Electronics Co., Ltd.

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Ha-Young JEON ,  Byung-Kwon CHO ,  Jeong-Nam HAN

IPC分类号： H01L29/66 ,  H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

摘要翻译： 半导体器件包括限定沟槽的栅极间隔。 沟槽包括顺序地位于基板上的第一部分和第二部分。 第一部分的内表面具有锐角的斜面，并且第二部分的内表面具有相对于基底的直角或钝角的斜率。 栅电极填充沟槽的至少一部分。