公开(公告)号：US20150137325A1

公开(公告)日：2015-05-21

申请号：US14329749

申请日：2014-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan HONG ,  Byung-Lyul PARK ,  Ji-Soon PARK ,  Si-Young CHOI

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/80894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.

Abstract translation: 提供一种半导体器件。 半导体器件包括在衬底的第一表面上限定金属图案的钝化层，设置在衬底的第二表面上的层间绝缘层，以及形成在金属图案和第一钝化层之间的压电图案 基板的表面。 通过硅通孔和/或焊盘可以仅通过施加压力而不进行热处理直接结合到另一个通硅通孔和/或另一焊盘。

公开(公告)号：US20190037443A1

公开(公告)日：2019-01-31

申请号：US16043761

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Hyung-Ho LEE ,  Sae-Woong BAHK ,  Si-Young CHOI ,  Seong-Joon KANG ,  Dong-Yeon WOO

IPC: H04W28/08 ,  H04W28/02 ,  H04L12/801

Abstract: The present disclosure provides methods and apparatus relating to a 5G or pre-5G communication system for supporting a higher data rate than that of a 4G communication system, such as long term evolution (LTE). A method for processing traffic at a core network entity processes traffic includes transmitting a message for requesting assistance information to at least one base station, receiving the assistance information from the at least one base station, splitting the traffic based on the received assistance information, and transmitting the split traffic through a core network. A core network entity includes a transceiver and a processor configured to control the transceiver to transmit a message for requesting assistance information to at least one base station, receive the assistance information from the at least one base station, split traffic based on the received assistance information, and transmit data through the split traffic.

公开(公告)号：US20160247925A1

公开(公告)日：2016-08-25

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US20160064380A1

公开(公告)日：2016-03-03

申请号：US14934119

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.