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    METHODS FOR FABRICATING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHODS FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20170040436A1

    公开(公告)日：2017-02-09

    申请号：US15191555

    申请日：2016-06-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seung-Jae LEE ,  Ja-Eung KOO ,  Ho-Young KIM ,  Yeong-Bong PARK ,  Il-Su PARK ,  Bo-Un YOON ,  Il-Young YOON ,  Youn-Su HA

    IPC分类号： H01L29/66 ,  H01L21/321 ,  H01L29/417 ,  H01L21/28

    CPC分类号： H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

    摘要： A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

    摘要翻译： 一种用于制造半导体器件的方法可以包括在衬底的第一区域中形成具有第一阈值电压的第一晶体管，在衬底的第二区域中形成具有小于第一阈值电压的第二阈值电压的第二晶体管，形成 在第三区域中的第三层间绝缘膜，并且平坦化第一晶体管，第二晶体管和第三层间绝缘膜。 第一晶体管可以包括具有第一高度的第一栅极电极和具有第一高度的第一层间绝缘膜，并且第二晶体管可以包括具有比第一高度短的第二高度的第二栅极电极和第二层间绝缘膜， 第二高度。 第三层间绝缘膜可以具有第一高度。

    METHOD OF FORMING A PLUG, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME, POLISHING CHAMBER USED FOR MANUFACTURING THE SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD OF FORMING A PLUG, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME, POLISHING CHAMBER USED FOR MANUFACTURING THE SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE 审中-公开
    形成插片的方法，制造使用其的半导体器件的方法，用于制造半导体器件的抛光室和半导体器件

    公开(公告)号：US20170040208A1

    公开(公告)日：2017-02-09

    申请号：US15142043

    申请日：2016-04-29

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seung-Hoon CHOI ,  Ho-Young KIM ,  Gi-Gwan PARK ,  Hyun-Kyung BAE ,  Bo-Un YOON ,  Il-Young YOON

    IPC分类号： H01L21/768

    CPC分类号： H01L21/7684 ,  B24B37/042 ,  H01L21/67219 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/41791

    摘要： A method of forming a plug and manufacturing a semiconductor device, a polishing chamber, and a semiconductor device, the method of forming a plug including forming an opening in an insulating interlayer pattern on a substrate; forming a metal layer to fill the opening; performing a first CMP process during a first time period until a top surface of the insulating interlayer pattern is exposed while pressing the substrate onto a first polishing pad to polish the metal layer; performing a second CMP process during a second time period while pressing the substrate onto a second polishing pad to polish the metal layer and the insulating interlayer pattern, so that a metal plug is formed in the insulating interlayer pattern; and performing a first cleaning process on the second polishing pad while keeping the substrate spaced apart from the second polishing pad on the second platen.

    摘要翻译： 一种形成插头并制造半导体器件，抛光室和半导体器件的方法，包括在衬底上形成绝缘层间图案中的开口的形成插头的方法; 形成金属层以填充开口; 在第一时间段内执行第一CMP处理直到绝缘层间图案的顶表面暴露，同时将基板压在第一抛光垫上以抛光金属层; 在第二时间段内执行第二CMP处理，同时将衬底按压到第二抛光垫上以抛光金属层和绝缘层间图案，从而在绝缘层间图案中形成金属插塞; 以及在所述第二台板上保持与所述第二抛光垫间隔开的所述基板的同时对所述第二抛光垫进行第一清洁处理。

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160365453A1

    公开(公告)日：2016-12-15

    申请号：US15168694

    申请日：2016-05-31

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ju-Hyun Kim ,  Ho-Young KIM ,  Se-Jung PARK ,  Bo-Un Yoon

    IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088

    CPC分类号： H01L29/7856 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7854

    摘要： A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.

    摘要翻译： 半导体器件包括在衬底上的第一鳍式图案，其具有彼此相对的第一侧壁和第二侧壁; 形成为与所述第一侧壁接触的第一沟槽; 形成为与第二侧壁接触的第二沟槽; 部分地填充所述第一沟槽的第一场绝缘层; 以及部分地填充所述第二沟槽的第二场绝缘层和部分地填充所述第二沟槽的第二场绝缘层。 第二场绝缘层包括从第二侧壁开始以顺序设置的第一区域和第二区域，第二区域的上表面高于第一场绝缘层的上表面。 该器件还包括在第一鳍型图案上的栅电极，第一场绝缘层和第二场绝缘层，栅电极与第一鳍型相交，并与第二区重叠。

    Methods of Fabricating Semiconductor Devices
    9.
    发明申请
    Methods of Fabricating Semiconductor Devices 有权
    制造半导体器件的方法

    公开(公告)号：US20160104788A1

    公开(公告)日：2016-04-14

    申请号：US14815225

    申请日：2015-07-31

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yeon-Tack RYU ,  Ho-Young KIM ,  Myoung-Hwan OH ,  Bo-Un YOON ,  Jun-Hwan YIM

    IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/283

    CPC分类号： H01L29/66545 ,  H01L21/31053 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    摘要： Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask.

    摘要翻译： 提供了制造半导体器件的半导体器件和方法。 所述方法可以包括在基底上形成层间绝缘层。 层间绝缘层可以包围虚拟硅栅极并且可以暴露虚拟硅栅极的顶表面。 所述方法还可以包括使所述层间绝缘层的一部分凹陷，使得所述虚拟硅栅极的一部分突出于所述凹陷层间绝缘层的顶表面之上，并在所述凹陷层间绝缘层上形成蚀刻停止层。 蚀刻停止层的顶表面可以与虚拟硅栅极的顶表面共面定位。 所述方法还可以包括通过使用蚀刻停止层作为掩模去除伪硅栅极来形成暴露衬底的沟槽。