公开(公告)号：US20170040436A1

公开(公告)日：2017-02-09

申请号：US15191555

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jae LEE ,  Ja-Eung KOO ,  Ho-Young KIM ,  Yeong-Bong PARK ,  Il-Su PARK ,  Bo-Un YOON ,  Il-Young YOON ,  Youn-Su HA

IPC: H01L29/66 ,  H01L21/321 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Abstract translation: 一种用于制造半导体器件的方法可以包括在衬底的第一区域中形成具有第一阈值电压的第一晶体管，在衬底的第二区域中形成具有小于第一阈值电压的第二阈值电压的第二晶体管，形成 在第三区域中的第三层间绝缘膜，并且平坦化第一晶体管，第二晶体管和第三层间绝缘膜。 第一晶体管可以包括具有第一高度的第一栅极电极和具有第一高度的第一层间绝缘膜，并且第二晶体管可以包括具有比第一高度短的第二高度的第二栅极电极和第二层间绝缘膜， 第二高度。 第三层间绝缘膜可以具有第一高度。