公开(公告)号：US20170162675A1

公开(公告)日：2017-06-08

申请号：US15361516

申请日：2016-11-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jun-Hwan YIM ,  Yeon-Tack RYU ,  Joo-Cheol HAN ,  Ja-Eung KOO ,  No-Ul KIM ,  Ho-Young KIM ,  Bo-Un YOON

IPC分类号： H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.