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    SPIN MOSFET
    1.
    发明申请
    SPIN MOSFET 审中-公开

    公开(公告)号：US20150311305A1

    公开(公告)日：2015-10-29

    申请号：US14793173

    申请日：2015-07-07

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Yoshiaki SAITO

    IPC分类号： H01L29/45 ,  H01L29/82 ,  H01L29/08 ,  H01L29/66

    CPC分类号： H01L29/45 ,  G11C11/161 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/41725 ,  H01L29/66227 ,  H01L29/66984 ,  H01L29/82

    摘要： An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum.

    摘要翻译： 根据实施例的MOSFET包括：源极和漏极，每个包括磁性层; 栅极绝缘膜; 以及设置在所述栅极绝缘膜上的栅电极，在所述MOSFET为n沟道型时，所述源电极侧的结电阻大于所述漏电极侧的结电阻，所述源电极和漏极包含磁性材料，其中， 费米表面和价带最大值之间的间隙能量大于费米表面和导带最小值之间的间隙能量，并且当自旋转移 - 转矩开关MOSFET是p沟道型时，源极和漏极包含 费米表面和价带最大值之间的间隙能量小于费米表面和导带最小值之间的磁性材料。

    SPIN TRANSISTOR MEMORY
    2.
    发明申请
    SPIN TRANSISTOR MEMORY 有权
    旋转晶体管存储器

    公开(公告)号：US20160276007A1

    公开(公告)日：2016-09-22

    申请号：US15063808

    申请日：2016-03-08

    申请人： Kabushiki Kaisha Toshiba

    发明人： Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

    IPC分类号： G11C11/16 ,  H01L29/82 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

    CPC分类号： G11C11/161 ,  G11C11/15 ,  G11C11/165 ,  H01L29/66984 ,  H03K19/18

    摘要： A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

    摘要翻译： 根据实施例的自旋晶体管存储器包括：第一半导体区域，第二半导体区域和第三半导体区域，每个都是第一导电类型并且设置在半导体层中; 设置在所述第一半导体区域和所述第二半导体区域之间的所述半导体层上方的第一栅极; 设置在所述第二半导体区域和所述第三半导体区域之间的所述半导体层上方的第二栅极; 以及分别设置在第一半导体区域，第二半导体区域和第三半导体区域上的第一铁磁层，第二铁磁层和第三铁磁层。

    RESISTIVE CHANGE MEMORY
    4.
    发明申请
    RESISTIVE CHANGE MEMORY 有权
    电阻变化记忆

    公开(公告)号：US20150357016A1

    公开(公告)日：2015-12-10

    申请号：US14832520

    申请日：2015-08-21

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Tomoaki INOKUCHI ,  Mizue ISHIKAWA ,  Hideyuki SUGIYAMA ,  Yoshiaki SAITO ,  Tetsufumi TANAMOTO

    IPC分类号： G11C11/16

    CPC分类号： G11C11/161 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08

    摘要： A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.

    摘要翻译： 根据实施例的电阻变化存储器包括：存储单元，包括包括第一和第二端子的电阻变化元件和半导体元件，所述半导体元件包括第一导电类型的第一半导体层，第二半导体层 第一导电类型和与第一导电类型不同的第二导电类型的第三半导体层，第三半导体层设置在第一半导体层和第二半导体层之间，第一半导体层连接到第二导体类型 的电阻变化元件; 以及读取单元，被配置为通过在第一端子和第二半导体层之间施加第一读取电压来执行读取操作，然后在第一端子和第二半导体层之间施加低于第一读取电压的第二读取电压 。

    STACKED STRUCTURE, SPIN TRANSISTOR, AND RECONFIGURABLE LOGIC CIRCUIT
    5.
    发明申请
    STACKED STRUCTURE, SPIN TRANSISTOR, AND RECONFIGURABLE LOGIC CIRCUIT 有权
    堆叠结构，旋转晶体管和可重新配置的逻辑电路

    公开(公告)号：US20140117427A1

    公开(公告)日：2014-05-01

    申请号：US14041055

    申请日：2013-09-30

    申请人： Kabushiki Kaisha Toshiba

    发明人： Yoshiaki SAITO ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Tetsufumi Tanamoto

    IPC分类号： H01L43/10

    CPC分类号： H01L43/10 ,  H01L29/66984 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/18

    摘要： A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.

    摘要翻译： 根据实施例的堆叠结构包括：半导体层; 形成在所述半导体层上的第一层，所述第一层含有选自Zr，Ti和Hf中的至少一种元素，所述第一层不比单原子层薄，并且不比五原子层厚; 形成在所述第一层上的隧道势垒层; 以及形成在隧道势垒层上的磁性层。

    MAGNETIC MEMORY DEVICE
    6.
    发明申请
    MAGNETIC MEMORY DEVICE 审中-公开

    公开(公告)号：US20190080741A1

    公开(公告)日：2019-03-14

    申请号：US15918000

    申请日：2018-03-12

    申请人： Kabushiki Kaisha Toshiba

    发明人： Yushi KATO ,  Yoshiaki SAITO ,  Mizue ISHIKAWA ,  Soichi OIKAWA ,  Hiroaki YODA

    IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01F10/32 ,  G11C11/18

    摘要： According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, and a controller. The conductive layer includes first and second portions, and a third portion between the first and second portions. The conductive layer includes a first metal and boron. The first magnetic layer is separated from the third portion in a first direction crossing a second direction. The second magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second portions. The controller supplies a current to the conductive layer. The first metal includes at least one selected from the group consisting of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

    MAGNETIC MEMORY
    9.
    发明申请
    MAGNETIC MEMORY 审中-公开

    公开(公告)号：US20190066749A1

    公开(公告)日：2019-02-28

    申请号：US16177186

    申请日：2018-10-31

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Hiroaki YODA ,  Naoharu SHIMOMURA ,  Yoshiaki SAITO ,  Yuichi OHSAWA ,  Keiko ABE

    IPC分类号： G11C11/16

    摘要： A magnetic memory includes: first to third terminals; a conductive layer including first to fifth regions, the first region being electrically connected to the first terminal, the fifth region being electrically connected to the second terminal, and the third region being electrically connected to the third terminal; a first magnetoresistive element including a first magnetic layer, a second magnetic layer disposed between the second region and the first magnetic layer, and a first nonmagnetic layer disposed between the first and the second magnetic layer; a second magnetoresistive element including a third magnetic layer, a fourth magnetic layer disposed between the fourth region and the third magnetic layer, and a second nonmagnetic layer disposed between the third and the fourth magnetic layer; and a circuit flowing a write current between the first and the second terminal and between the second and the third terminal in a write operation.

    MAGNETIC MEMORY
    10.
    发明申请
    MAGNETIC MEMORY 审中-公开

    公开(公告)号：US20180268886A1

    公开(公告)日：2018-09-20

    申请号：US15691991

    申请日：2017-08-31

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Mizue ISHIKAWA ,  Yushi KATO ,  Yoshiaki SAITO ,  Soichi OIKAWA ,  Hiroaki YODA

    IPC分类号： G11C11/16 ,  G11C5/08 ,  H01L27/22 ,  G11C11/18 ,  H01L43/04 ,  H01L43/10

    CPC分类号： G11C11/161 ,  G11C5/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/226 ,  H01L43/04 ,  H01L43/10

    摘要： A magnetic memory of an embodiment includes: first through third terminals; a conductive layer including first through third portions, the first portion being located between the second and third portions, the second and third portions being electrically connected to the first and second terminals respectively; and a magnetoresistive element including: a first magnetic layer electrically connected to the third terminal; a second magnetic layer disposed between the first magnetic layer and the first portion; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first nonmagnetic layer and the second magnetic layer; and a second nonmagnetic layer disposed between the second magnetic layer and the third magnetic layer, a sign of a spin Hall angle of the second nonmagnetic layer being different from a sign of a spin Hall angle of the conductive layer.