公开(公告)号：US10510949B2

公开(公告)日：2019-12-17

申请号：US16119553

申请日：2018-08-31

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mariko Shimizu ,  Yuichi Ohsawa ,  Hiroaki Yoda ,  Hideyuki Sugiyama ,  Satoshi Shirotori ,  Altansargai Buyandalai

IPC: G11C11/00 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory device includes a metal-containing layer, a first magnetic layer, a second magnetic layer, a first intermediate layer, a third magnetic layer, a fourth magnetic layer, a second intermediate layer, and a controller. The metal-containing layer includes first, second, third, fourth, and fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the first magnetic layer and a portion of the third portion. The first intermediate layer includes a portion provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the third magnetic layer and a portion of the fourth portion. The second intermediate layer includes a portion provided between the third and fourth magnetic layers. The controller is electrically connected with the first portion and the second portion.

公开(公告)号：US10483459B2

公开(公告)日：2019-11-19

申请号：US15914206

申请日：2018-03-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hideyuki Sugiyama ,  Yuichi Ohsawa ,  Satoshi Shirotori ,  Mariko Shimizu ,  Altansargai Buyandalai ,  Hiroaki Yoda

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22 ,  G11C11/18 ,  H01L43/10

Abstract: A magnetic memory according to an embodiment includes: a first conductive layer including a first to third regions arranged along a first direction, the second region being disposed between the first region and the third region; a second conductive layer including a fourth to sixth regions arranged along the first direction, the fifth region being disposed between the fourth and sixth regions; a third conductive layer electrically connected to the third and fourth regions; a first magnetoresistance device disposed to correspond to the second region, including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second magnetoresistance device to correspond to the fifth region, including a third magnetic layer, a fourth magnetic layer, and a second nonmagnetic layer, a direction from the first region to the third region differing from a direction from the fourth region to the sixth region.

公开(公告)号：US10283697B2

公开(公告)日：2019-05-07

申请号：US15266598

申请日：2016-09-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  G11C11/18

Abstract: A magnetic memory according to an embodiment includes: a magnetoresistive device including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer between the first magnetic layer and the second magnetic layer; a first wiring electrically connected to the first magnetic layer; a second wiring that is electrically connected to the second magnetic layer and contains an antiferromagnetic material; a third wiring crossing the second wiring; an insulating layer between the second wiring and the third wiring; a first write circuit for applying a voltage between the second wiring and the third wiring; and a read circuit electrically connected to the first wiring and the second wiring.

公开(公告)号：US20140117427A1

公开(公告)日：2014-05-01

申请号：US14041055

申请日：2013-09-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yoshiaki SAITO ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Tetsufumi Tanamoto

IPC: H01L43/10

CPC classification number: H01L43/10 ,  H01L29/66984 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/18

Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.

Abstract translation: 根据实施例的堆叠结构包括：半导体层; 形成在所述半导体层上的第一层，所述第一层含有选自Zr，Ti和Hf中的至少一种元素，所述第一层不比单原子层薄，并且不比五原子层厚; 形成在所述第一层上的隧道势垒层; 以及形成在隧道势垒层上的磁性层。

公开(公告)号：US20130248941A1

公开(公告)日：2013-09-26

申请号：US13749982

申请日：2013-01-25

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito

IPC: H01L29/82

CPC classification number: H01L29/82 ,  G11C11/161 ,  G11C11/1675 ,  H01L29/66984

Abstract: A spin transistor according to an embodiment includes: a semiconductor layer including a p+-region and an n+-region located at a distance from each other, and an i-region located between the p+-region and the n+-region; a first electrode located on the p+-region, the first electrode including a first ferromagnetic layer; a second electrode located on the n+-region, the second electrode including a second ferromagnetic layer; and a gate located on at least the i-region.

Abstract translation: 根据实施例的自旋晶体管包括：包括彼此相距一定距离的p +区和n +区的半导体层和位于p +区和n +区之间的i区; 位于所述p +区上的第一电极，所述第一电极包括第一铁磁层; 位于所述n +区域上的第二电极，所述第二电极包括第二铁磁层; 以及至少位于i区域的门。

公开(公告)号：US11127895B2

公开(公告)日：2021-09-21

申请号：US16684683

申请日：2019-11-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi Shirotori ,  Yuichi Ohsawa ,  Hideyuki Sugiyama ,  Altansargai Buyandalai ,  Mariko Shimizu ,  Hiroaki Yoda

IPC: H01L43/02 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory device includes a first insulating region, a first counter insulating region, a first conductive member, and a first magnetic element. The first conductive member is provided between the first insulating region and the first counter insulating region. The first conductive member extends in a first direction crossing a second direction. The second direction is from the first insulating region toward the first counter insulating region. The first magnetic element is provided between the first insulating region and the first counter insulating region. A third direction from the first conductive member toward the first magnetic element crosses a plane including the first and second directions. A portion of a first insulating side surface of the first insulating region opposes the first conductive member. A portion of a first counter insulating side surface of the first counter insulating region opposes the first conductive member.

公开(公告)号：US10916281B2

公开(公告)日：2021-02-09

申请号：US16299861

申请日：2019-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hideyuki Sugiyama ,  Kazutaka Ikegami ,  Naoharu Shimomura

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/10

Abstract: According to one embodiment, a magnetic memory apparatus includes a first stacked body and a controller. The first stacked body includes a first magnetic layer, a first counter magnetic layer, and a first intermediate layer placed between the first magnetic layer and the first counter magnetic layer. The first intermediate layer is nonmagnetic. The controller is electrically connected to the first magnetic layer and the first counter magnetic layer. The controller is configured to perform a first operation of supplying first pulse current to the first stacked body. The first pulse current includes a first constant-current period. A first electrical resistance value of the first stacked body before the supply of the first pulse current is different from a second electrical resistance value of the first stacked body after the supply of the first pulse current.

公开(公告)号：US10347313B2

公开(公告)日：2019-07-09

申请号：US15915654

申请日：2018-03-08

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Naoharu Shimomura ,  Tomoaki Inokuchi ,  Katsuhiko Koui ,  Yuzo Kamiguchi ,  Hiroaki Yoda ,  Hideyuki Sugiyama

IPC: G11C11/16 ,  H01L43/08 ,  G11C11/18 ,  H01L27/22 ,  H01L43/06

Abstract: According to one embodiment, a magnetic memory includes: magnetoresistive effect elements arranged on an conductive layer; and a first circuit which passes a write current through the conductive layer and applies a control voltage to the magnetoresistive effect elements, to write data including a first value and a second value into the magnetoresistive effect elements. The first circuit adjusts at least one of a write sequence of the first value and the second value, a current value of the write current, and a pulse width of the write current, on the basis of an arrangement of the first value and the second value in the data.

公开(公告)号：US10276786B2

公开(公告)日：2019-04-30

申请号：US15905907

申请日：2018-02-27

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yuichi Ohsawa ,  Mariko Shimizu ,  Satoshi Shirotori ,  Hideyuki Sugiyama ,  Altansargai Buyandalai ,  Hiroaki Yoda

IPC: G11C11/00 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: According to one embodiment, a magnetic memory device includes a first conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a second conductive layer, a third magnetic layer, a second nonmagnetic layer, a fourth magnetic layer provided, a first compound region, and a first insulating region. The first compound region includes the first metal and at least one selected from the group consisting of oxygen, nitrogen, and fluorine. At least a portion of the first compound region is provided between the first conductive layer and the second conductive layer. The first insulating region includes at least one selected from the group consisting of Al and Si and at least one selected from the group consisting of oxygen, nitrogen, and fluorine. At least a portion of the first insulating region is provided between the first magnetic layer and the third magnetic layer.

公开(公告)号：US10170694B1

公开(公告)日：2019-01-01

申请号：US15911341

申请日：2018-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi Shirotori ,  Yuichi Ohsawa ,  Hideyuki Sugiyama ,  Mariko Shimizu ,  Altansargai Buyandalai ,  Naoharu Shimomura ,  Katsuhiko Koui ,  Tomoaki Inokuchi ,  Hiroaki Yoda

IPC: H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: A magnetic memory of an embodiment includes: a first conductive layer, which is nonmagnetic and includes at least a first element, the first conductive layer including a first to fifth regions; a first magnetoresistive element disposed corresponding to the third region and including a first magnetic layer, a second magnetic layer including at least a second element, a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, a second nonmagnetic layer disposed between the second magnetic layer and the first nonmagnetic layer and including at least a third element, and a third magnetic layer disposed between the second nonmagnetic layer and the first nonmagnetic layer; a second conductive layer disposed corresponding to the second region and including at least the first to third elements; and a third conductive layer disposed corresponding to the fourth region, and including at least the first to third elements.