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公开(公告)号:US20150311305A1
公开(公告)日:2015-10-29
申请号:US14793173
申请日:2015-07-07
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Mizue ISHIKAWA , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Yoshiaki SAITO
CPC classification number: H01L29/45 , G11C11/161 , H01L29/0847 , H01L29/0895 , H01L29/41725 , H01L29/66227 , H01L29/66984 , H01L29/82
Abstract: An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum.
Abstract translation: 根据实施例的MOSFET包括:源极和漏极,每个包括磁性层; 栅极绝缘膜; 以及设置在所述栅极绝缘膜上的栅电极,在所述MOSFET为n沟道型时,所述源电极侧的结电阻大于所述漏电极侧的结电阻,所述源电极和漏极包含磁性材料,其中, 费米表面和价带最大值之间的间隙能量大于费米表面和导带最小值之间的间隙能量,并且当自旋转移 - 转矩开关MOSFET是p沟道型时,源极和漏极包含 费米表面和价带最大值之间的间隙能量小于费米表面和导带最小值之间的磁性材料。
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2.
公开(公告)号:US20160078913A1
公开(公告)日:2016-03-17
申请号:US14948709
申请日:2015-11-23
Applicant: Kabushiki Kaisha Toshiba
Inventor: Tomoaki INOKUCHI , Mizue ISHIKAWA , Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Akira TAKASHIMA , Yoshiaki SAITO
IPC: G11C11/16
CPC classification number: G11C11/161 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/2275 , G11C11/5607 , G11C13/0069 , G11C19/0808 , H01L27/222 , H01L27/224 , H01L29/66984 , H01L29/82 , H01L43/08
Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.
Abstract translation: 根据实施例的磁存储器包括:包括半导体层和第一铁磁层的多层结构; 电连接到所述半导体层的第一布线; 电连接到第一铁磁层的第二布线; 以及电压施加单元,电连接在第一布线和第二布线之间,以在写入操作期间在半导体层和第一铁磁层之间施加第一电压,第一铁磁层的磁化方向可通过施加第一 电压。
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公开(公告)号:US20150357016A1
公开(公告)日:2015-12-10
申请号:US14832520
申请日:2015-08-21
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Tomoaki INOKUCHI , Mizue ISHIKAWA , Hideyuki SUGIYAMA , Yoshiaki SAITO , Tetsufumi TANAMOTO
IPC: G11C11/16
CPC classification number: G11C11/161 , G11C11/15 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C2213/72 , G11C2213/74 , G11C2213/79 , H01L27/224 , H01L27/228 , H01L43/08
Abstract: A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.
Abstract translation: 根据实施例的电阻变化存储器包括:存储单元,包括包括第一和第二端子的电阻变化元件和半导体元件,所述半导体元件包括第一导电类型的第一半导体层,第二半导体层 第一导电类型和与第一导电类型不同的第二导电类型的第三半导体层,第三半导体层设置在第一半导体层和第二半导体层之间,第一半导体层连接到第二导体类型 的电阻变化元件; 以及读取单元,被配置为通过在第一端子和第二半导体层之间施加第一读取电压来执行读取操作,然后在第一端子和第二半导体层之间施加低于第一读取电压的第二读取电压 。
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公开(公告)号:US20190080741A1
公开(公告)日:2019-03-14
申请号:US15918000
申请日:2018-03-12
Applicant: Kabushiki Kaisha Toshiba
Inventor: Yushi KATO , Yoshiaki SAITO , Mizue ISHIKAWA , Soichi OIKAWA , Hiroaki YODA
Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, and a controller. The conductive layer includes first and second portions, and a third portion between the first and second portions. The conductive layer includes a first metal and boron. The first magnetic layer is separated from the third portion in a first direction crossing a second direction. The second magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second portions. The controller supplies a current to the conductive layer. The first metal includes at least one selected from the group consisting of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
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公开(公告)号:US20180174634A1
公开(公告)日:2018-06-21
申请号:US15700485
申请日:2017-09-11
Applicant: Kabushiki Kaisha Toshiba
Inventor: Yushi KATO , Soichi OIKAWA , Mizue ISHIKAWA , Yoshiaki SAITO , Hiroaki YODA
CPC classification number: G11C11/15 , G11C11/155 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/5685 , H01L27/228 , H01L43/04 , H01L43/08 , H01L43/10 , H01L43/14
Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, and a controller. The conductive layer includes a first portion, a second portion, and a third portion between the first and second portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second portions. The third portion includes a first region and a second region. The second region is provided between the first region and the second magnetic layer. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
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公开(公告)号:US20170271574A1
公开(公告)日:2017-09-21
申请号:US15266598
申请日:2016-09-15
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Tomoaki INOKUCHI , Mizue ISHIKAWA , Hideyuki SUGIYAMA , Yoshiaki SAITO
CPC classification number: H01L43/02 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/18 , H01L27/222 , H01L43/08 , H01L43/10
Abstract: A magnetic memory according to an embodiment includes: a magnetoresistive device including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer between the first magnetic layer and the second magnetic layer; a first wiring electrically connected to the first magnetic layer; a second wiring that is electrically connected to the second magnetic layer and contains an antiferromagnetic material; a third wiring crossing the second wiring; an insulating layer between the second wiring and the third wiring; a first write circuit for applying a voltage between the second wiring and the third wiring; and a read circuit electrically connected to the first wiring and the second wiring.
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公开(公告)号:US20200058338A1
公开(公告)日:2020-02-20
申请号:US16272372
申请日:2019-02-11
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Mizue ISHIKAWA , Yushi KATO , Soichi OIKAWA , Hiroaki YODA
Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive member includes a first layer. The first layer includes at least one selected from the group consisting of HfN having a NaCl structure, HfN having a fcc structure, and HfC having a NaCl structure. The first magnetic layer is separated from the first layer in a first direction. The second magnetic layer is provided between the first layer and the first magnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer.
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公开(公告)号:US20160276007A1
公开(公告)日:2016-09-22
申请号:US15063808
申请日:2016-03-08
Applicant: Kabushiki Kaisha Toshiba
Inventor: Hideyuki SUGIYAMA , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO
CPC classification number: G11C11/161 , G11C11/15 , G11C11/165 , H01L29/66984 , H03K19/18
Abstract: A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.
Abstract translation: 根据实施例的自旋晶体管存储器包括:第一半导体区域,第二半导体区域和第三半导体区域,每个都是第一导电类型并且设置在半导体层中; 设置在所述第一半导体区域和所述第二半导体区域之间的所述半导体层上方的第一栅极; 设置在所述第二半导体区域和所述第三半导体区域之间的所述半导体层上方的第二栅极; 以及分别设置在第一半导体区域,第二半导体区域和第三半导体区域上的第一铁磁层,第二铁磁层和第三铁磁层。
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公开(公告)号:US20180268886A1
公开(公告)日:2018-09-20
申请号:US15691991
申请日:2017-08-31
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Mizue ISHIKAWA , Yushi KATO , Yoshiaki SAITO , Soichi OIKAWA , Hiroaki YODA
CPC classification number: G11C11/161 , G11C5/08 , G11C11/1659 , G11C11/1675 , G11C11/18 , H01L27/226 , H01L43/04 , H01L43/10
Abstract: A magnetic memory of an embodiment includes: first through third terminals; a conductive layer including first through third portions, the first portion being located between the second and third portions, the second and third portions being electrically connected to the first and second terminals respectively; and a magnetoresistive element including: a first magnetic layer electrically connected to the third terminal; a second magnetic layer disposed between the first magnetic layer and the first portion; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first nonmagnetic layer and the second magnetic layer; and a second nonmagnetic layer disposed between the second magnetic layer and the third magnetic layer, a sign of a spin Hall angle of the second nonmagnetic layer being different from a sign of a spin Hall angle of the conductive layer.
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10.
公开(公告)号:US20140301136A1
公开(公告)日:2014-10-09
申请号:US14204422
申请日:2014-03-11
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Tomoaki INOKUCHI , Mizue ISHIKAWA , Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Akira TAKASHIMA , Yoshiaki SAITO
CPC classification number: G11C11/161 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/2275 , G11C11/5607 , G11C13/0069 , G11C19/0808 , H01L27/222 , H01L27/224 , H01L29/66984 , H01L29/82 , H01L43/08
Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.
Abstract translation: 根据实施例的磁存储器包括:包括半导体层和第一铁磁层的多层结构; 电连接到所述半导体层的第一布线; 电连接到第一铁磁层的第二布线; 以及电压施加单元,电连接在第一布线和第二布线之间,以在写入操作期间在半导体层和第一铁磁层之间施加第一电压,第一铁磁层的磁化方向可通过施加第一 电压。
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