公开(公告)号：US20180211154A1

公开(公告)日：2018-07-26

申请号：US15685042

申请日：2017-08-24

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masafumi MORI ,  Takao MARUKAME ,  Tetsufumi TANAMOTO ,  Satoshi TAKAYA

IPC: G06N3/04

CPC classification number: G06N3/0445 ,  G06N3/0472 ,  G06N3/063

Abstract: According to an emboediment, a multiplier accumurator includes a controller, a high-order multiplier, a high-order accumulator, a low-order multiplier, and an output unit. The controller is configured to designate each digit within a range of the most significant digit in a coefficient for an input value to a stop digit as a target digit. The high-order multiplier is configured to calculate a high-order multiplication value by multiplying the input value, and a value and a weight of the target digit. The high-order accumulator is configured to calculate a high-order accumulation value by accumulatively adding the high-order multiplication values for input values. The low-order multiplier is configured to calculate a low-order multiplication value by multiplying an input value and a value of a digit smaller than the stop digit. The output unit is configured to output a value determined based on whether the high-order accumulation value exceeds a boundary value.

公开(公告)号：US20170272258A1

公开(公告)日：2017-09-21

申请号：US15256783

申请日：2016-09-06

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tetsufumi TANAMOTO ,  Shinobu FUJITA

IPC: H04L9/32 ,  G11C11/16

CPC classification number: H04L9/3278 ,  G11C11/1673 ,  G11C11/1675 ,  H04L9/0866

Abstract: A data generation apparatus according to an embodiment comprises a memory space including a plurality of memory cells, each including a resistance change element, a first circuit configured to supply the memory cells included in a first space that represents part of the memory space with a current or a voltage that causes a dielectric breakdown to occur in the resistance change element, a second circuit configured to output a value read from the memory cells included in the first space, and an ID generation circuit configured to generate an ID using the value output from the second circuit.

公开(公告)号：US20150311305A1

公开(公告)日：2015-10-29

申请号：US14793173

申请日：2015-07-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Yoshiaki SAITO

IPC: H01L29/45 ,  H01L29/82 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/45 ,  G11C11/161 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/41725 ,  H01L29/66227 ,  H01L29/66984 ,  H01L29/82

Abstract: An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum.

Abstract translation: 根据实施例的MOSFET包括：源极和漏极，每个包括磁性层; 栅极绝缘膜; 以及设置在所述栅极绝缘膜上的栅电极，在所述MOSFET为n沟道型时，所述源电极侧的结电阻大于所述漏电极侧的结电阻，所述源电极和漏极包含磁性材料，其中， 费米表面和价带最大值之间的间隙能量大于费米表面和导带最小值之间的间隙能量，并且当自旋转移 - 转矩开关MOSFET是p沟道型时，源极和漏极包含 费米表面和价带最大值之间的间隙能量小于费米表面和导带最小值之间的磁性材料。

公开(公告)号：US20140372671A1

公开(公告)日：2014-12-18

申请号：US14190463

申请日：2014-02-26

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tetsufumi TANAMOTO ,  Takao Marukame ,  Shinichi Yasuda ,  Yuichiro Mitani ,  Atsushi Shimbo ,  Tatsuya Kishi

IPC: G06F12/14

CPC classification number: G06F21/73 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  G11C13/0035 ,  G11C16/10 ,  G11C16/349

Abstract: According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit.

Abstract translation: 根据实施例，认证装置包括获取单元，预测单元和认证单元。 获取单元被配置为获取作为要认证的设备的第一设备的性能信息。 预测单元被配置为根据与初始性能信息随时间的变化来预测作为用于认证的参考的设备的第二设备的性能信息。 认证单元被配置为基于由获取单元获取的演奏信息与由预测单元预测的演奏信息之间的一致性来执行确定第一设备是否落入第二设备的认证处理。

公开(公告)号：US20200089470A1

公开(公告)日：2020-03-19

申请号：US16289098

申请日：2019-02-28

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MEMORY CORPORATION

Inventor： Tetsufumi TANAMOTO ,  Yoshifumi NISHI ,  Jun DEGUCHI

IPC: G06F7/22 ,  G06N10/00

Abstract: According to an embodiment, a quantum annealing apparatus includes: an output unit acquiring and outputting components in a Z axis from a plurality of quantum bits in a quantum calculation; and an operation unit executes: a selecting process of selecting a first quantum bit, a second quantum bit and a third quantum bit, the second quantum bit and the third quantum bit being coupled in the quantum calculation unit; a first rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a first axis perpendicular to the Z axis; an interaction operation of causing the first quantum bit and the second quantum bit to interact with each other; and a second rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a second axis perpendicular to the Z axis and the first axis.

公开(公告)号：US20180076965A1

公开(公告)日：2018-03-15

申请号：US15443228

申请日：2017-02-27

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tetsufumi TANAMOTO ,  Shinichi YASUDA ,  Satoshi TAKAYA ,  Masafumi MORI ,  Takao MARUKAME

IPC: H04L9/32 ,  H04L29/06

CPC classification number: H04L9/3278 ,  H04L63/0876

Abstract: An authentication server according to embodiments performs statistical processing on a plurality of pieces of ID data acquired from an electronic device including a PUF circuit generating the pieces of ID data (S1052 to S1071), determines whether the plurality of pieces of ID data are physical random numbers based on a result of the statistical processing (S1072), and when the plurality of pieces of ID data are determined to be physical random numbers, recognizes the result of authentication of the electronic device as a success of authentication (S1073), and when the plurality of pieces of ID data are determined not to be physical random numbers, recognizes a result of authentication of the electronic device as a failure of authentication (S1074).

公开(公告)号：US20160078913A1

公开(公告)日：2016-03-17

申请号：US14948709

申请日：2015-11-23

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tomoaki INOKUCHI ,  Mizue ISHIKAWA ,  Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Akira TAKASHIMA ,  Yoshiaki SAITO

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/2275 ,  G11C11/5607 ,  G11C13/0069 ,  G11C19/0808 ,  H01L27/222 ,  H01L27/224 ,  H01L29/66984 ,  H01L29/82 ,  H01L43/08

Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.

Abstract translation: 根据实施例的磁存储器包括：包括半导体层和第一铁磁层的多层结构; 电连接到所述半导体层的第一布线; 电连接到第一铁磁层的第二布线; 以及电压施加单元，电连接在第一布线和第二布线之间，以在写入操作期间在半导体层和第一铁磁层之间施加第一电压，第一铁磁层的磁化方向可通过施加第一 电压。

公开(公告)号：US20150357016A1

公开(公告)日：2015-12-10

申请号：US14832520

申请日：2015-08-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki INOKUCHI ,  Mizue ISHIKAWA ,  Hideyuki SUGIYAMA ,  Yoshiaki SAITO ,  Tetsufumi TANAMOTO

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08

Abstract: A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.

Abstract translation: 根据实施例的电阻变化存储器包括：存储单元，包括包括第一和第二端子的电阻变化元件和半导体元件，所述半导体元件包括第一导电类型的第一半导体层，第二半导体层 第一导电类型和与第一导电类型不同的第二导电类型的第三半导体层，第三半导体层设置在第一半导体层和第二半导体层之间，第一半导体层连接到第二导体类型 的电阻变化元件; 以及读取单元，被配置为通过在第一端子和第二半导体层之间施加第一读取电压来执行读取操作，然后在第一端子和第二半导体层之间施加低于第一读取电压的第二读取电压 。

公开(公告)号：US20160371189A1

公开(公告)日：2016-12-22

申请号：US15257163

申请日：2016-09-06

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroki NOGUCHI ,  Tetsufumi TANAMOTO ,  Kazutaka IKEGAMI ,  Shinobu FUJITA

IPC: G06F12/0868 ,  G11C11/16 ,  G06F11/10

CPC classification number: G06F12/0868 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0895 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/608 ,  G11C11/1659 ,  G11C11/1675 ,  G11C2029/0411 ,  G11C2207/2245 ,  Y02D10/13

Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

Abstract translation: 高速缓存存储器具有数据高速缓存以存储每条高速缓存线的数据，存储要存储在数据高速缓存中的数据的地址信息的标签，高速缓存控制器，用于确定处理器的访问请求的地址是否满足地址信息 存储在标签中并且控制对数据高速缓存和标签的访问;以及写周期控制器，用于基于存储在数据高速缓冲存储器中的数据的读取错误的发生频率中的至少一个来控​​制在数据高速缓存中写入数据所需的时段 数据高速缓存和由于读取存储在数据高速缓存中的数据的延迟而导致的处理器性能的降低程度。

公开(公告)号：US20160277025A1

公开(公告)日：2016-09-22

申请号：US15068794

申请日：2016-03-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tetsufumi TANAMOTO ,  Shinichi YASUDA ,  Shinobu FUJITA

IPC: H03K19/003

CPC classification number: H03K19/003 ,  G06F7/588 ,  G09C1/00 ,  H03K3/0315 ,  H03K3/84 ,  H04L9/3278

Abstract: A data generating device according to embodiments comprises a ring oscillator, a flip-flop circuit and a generator. The flip-flop circuit includes a first terminal and a second terminal to each of which the ring oscillator output is inputted, and that determines a value of output of the ring oscillator. The generator generates an ID for authentication based on one or more values determined by the flip-flop circuit at the time when the ring oscillator is turned on.

Abstract translation: 根据实施例的数据产生装置包括环形振荡器，触发器电路和发生器。 触发器电路包括输入环形振荡器输出的第一端子和第二端子，并且确定环形振荡器的输出值。 在环形振荡器导通时，发生器基于由触发器电路确定的一个或多个值产生用于认证的ID。