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    NONVOLATILE SEMICONDUCTOR MEMORY
    3.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY 有权
    非易失性半导体存储器

    公开(公告)号：US20170076773A1

    公开(公告)日：2017-03-16

    申请号：US15266797

    申请日：2016-09-15

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Hiroki NOGUCHI ,  Shinobu FUJITA

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

    Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being electrically connected to the second terminal, and a driver electrically connected to the first and fourth terminals, applying one of a first potential and a second potential to the first terminal and the other of the first and second potentials to the fourth terminal in writing, and applying one of the first and second potentials to the first terminal and the other of the first and second potentials to the fourth terminal in reading.

    Abstract translation: 根据一个实施例，非易失性半导体存储器包括具有第一和第二端子的电阻变化元件，具有第三和第四端子的晶体管和控制端子，第三端子电连接到第二端子，以及驱动器电连接到 第一和第四端子，将第一电位和第二电位中的一个施加到第一端，第一和第二电位中的另一个写入第四端，并将第一和第二电位中的一个施加到第一端，以及 第一和第二电位的另一个到第四个终端阅读。

    NONVOLATILE MEMORY
    5.
    发明申请
    NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20180040358A1

    公开(公告)日：2018-02-08

    申请号：US15453626

    申请日：2017-03-08

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Hiroki NOGUCHI ,  Shinobu FUJITA

    IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

    CPC classification number: G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

    Abstract: According to one embodiment, a nonvolatile memory includes a first conductive line including a first portion, a second portion, a third portion between the first and second portions, and a fourth portion between the second and third portions, a first storage element including a first terminal connected to the third portion and a second terminal, a first transistor including a third terminal connected to the second terminal, a fourth terminal, and a first electrode controlling a first current path, a second storage element including a fifth terminal connected to the fourth portion and a sixth terminal, and a second transistor including a seventh terminal connected to the sixth terminal, an eighth terminal, and a second electrode controlling a second current path.

    CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM
    6.
    发明申请
    CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM 审中-公开
    缓存记忆系统和处理器系统

    公开(公告)号：US20170075808A1

    公开(公告)日：2017-03-16

    申请号：US15262692

    申请日：2016-09-12

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Hiroki NOGUCHI ,  Shinobu FUJITA

    IPC: G06F12/0811 ,  G06F12/123 ,  G06F12/0808

    CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0897 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/225 ,  G06F2212/62 ,  Y02D10/13

    Abstract: A cache memory system has a first cache memory, a second cache memory which comprises a nonvolatile memory capable of generating a plurality of regions having different access speeds and has access priority lower than the first cache memory, and a cache controller which carries out a control where data to be stored in the second cache memory is sorted to the plurality of regions and stored thereto in accordance with access conditions with respect to the first cache memory.

    Abstract translation: 高速缓冲存储器系统具有第一高速缓冲存储器，第二高速缓存存储器，其包括能够生成具有不同访问速度的多个区域的非易失性存储器，并且具有低于第一高速缓存存储器的访问优先级;以及高速缓存控制器，其执行控制 其中要存储在第二高速缓冲存储器中的数据被分类到多个区域并且根据关于第一高速缓冲存储器的访问条件被存储在其中。

    CACHE MEMORY AND PROCESSOR SYSTEM
    7.
    发明申请
    CACHE MEMORY AND PROCESSOR SYSTEM 审中-公开
    高速缓存存储器和处理器系统

    公开(公告)号：US20160371189A1

    公开(公告)日：2016-12-22

    申请号：US15257163

    申请日：2016-09-06

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Hiroki NOGUCHI ,  Tetsufumi TANAMOTO ,  Kazutaka IKEGAMI ,  Shinobu FUJITA

    IPC: G06F12/0868 ,  G11C11/16 ,  G06F11/10

    CPC classification number: G06F12/0868 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0895 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/608 ,  G11C11/1659 ,  G11C11/1675 ,  G11C2029/0411 ,  G11C2207/2245 ,  Y02D10/13

    Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

    Abstract translation: 高速缓存存储器具有数据高速缓存以存储每条高速缓存线的数据，存储要存储在数据高速缓存中的数据的地址信息的标签，高速缓存控制器，用于确定处理器的访问请求的地址是否满足地址信息 存储在标签中并且控制对数据高速缓存和标签的访问;以及写周期控制器，用于基于存储在数据高速缓冲存储器中的数据的读取错误的发生频率中的至少一个来控​​制在数据高速缓存中写入数据所需的时段 数据高速缓存和由于读取存储在数据高速缓存中的数据的延迟而导致的处理器性能的降低程度。

    DATA GENERATING DEVICE AND AUTHENTICATION SYSTEM
    8.
    发明申请
    DATA GENERATING DEVICE AND AUTHENTICATION SYSTEM 有权
    数据生成装置和认证系统

    公开(公告)号：US20160277025A1

    公开(公告)日：2016-09-22

    申请号：US15068794

    申请日：2016-03-14

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Tetsufumi TANAMOTO ,  Shinichi YASUDA ,  Shinobu FUJITA

    IPC: H03K19/003

    CPC classification number: H03K19/003 ,  G06F7/588 ,  G09C1/00 ,  H03K3/0315 ,  H03K3/84 ,  H04L9/3278

    Abstract: A data generating device according to embodiments comprises a ring oscillator, a flip-flop circuit and a generator. The flip-flop circuit includes a first terminal and a second terminal to each of which the ring oscillator output is inputted, and that determines a value of output of the ring oscillator. The generator generates an ID for authentication based on one or more values determined by the flip-flop circuit at the time when the ring oscillator is turned on.

    Abstract translation: 根据实施例的数据产生装置包括环形振荡器，触发器电路和发生器。 触发器电路包括输入环形振荡器输出的第一端子和第二端子，并且确定环形振荡器的输出值。 在环形振荡器导通时，发生器基于由触发器电路确定的一个或多个值产生用于认证的ID。

    STORAGE DEVICE INCLUDING MAGNETIC ELEMENTS
    9.
    发明申请
    STORAGE DEVICE INCLUDING MAGNETIC ELEMENTS 有权
    包含磁性元件的存储器件

    公开(公告)号：US20160276031A1

    公开(公告)日：2016-09-22

    申请号：US15067708

    申请日：2016-03-11

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Keiko ABE ,  Shinobu FUJITA

    IPC: G11C14/00

    CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/412

    Abstract: A storage device according to an embodiment includes: first and second magnetic elements each including: a reference layer connected to a third terminal; a first magnetic layer including first through third magnetic regions; a nonmagnetic layer; a second magnetic layer connected to a first terminal and the first magnetic region; and a third magnetic layer connected to a second terminal and the third magnetic region; a first inverter including a p-channel first transistor, an n-channel second transistor, a first input terminal connected to the second terminal of the second magnetic element, and a first output terminal connected to the first terminal of the first magnetic element; and a second inverter including a p-channel third transistor, an n-channel fourth transistor, a second input terminal connected to the second terminal of the first magnetic element, and a second output terminal connected to the first terminal of the second magnetic element.

    Abstract translation: 根据实施例的存储装置包括：第一和第二磁性元件，每个包括：连接到第三端子的参考层; 包括第一至第三磁性区域的第一磁性层; 非磁性层; 连接到第一端子和第一磁性区域的第二磁性层; 以及连接到第二端子和第三磁性区域的第三磁性层; 第一反相器，包括p沟道第一晶体管，n沟道第二晶体管，连接到第二磁性元件的第二端子的第一输入端子和连接到第一磁性元件的第一端子的第一输出端子; 以及第二反相器，包括p沟道第三晶体管，n沟道第四晶体管，连接到第一磁性元件的第二端子的第二输入端子和连接到第二磁性元件的第一端子的第二输出端子。

    SEMICONDUCTOR MEMORY
    10.
    发明申请
    SEMICONDUCTOR MEMORY 有权
    半导体存储器

    公开(公告)号：US20160196873A1

    公开(公告)日：2016-07-07

    申请号：US15070685

    申请日：2016-03-15

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Hiroki NOGUCHI ,  Shinobu FUJITA

    IPC: G11C13/00 ,  G11C11/16 ,  G11C11/419

    CPC classification number: G11C13/0002 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/419 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C2207/005

    Abstract: According to one embodiment, a semiconductor memory includes a first block array including first to n-th blocks (n is a natural number of 2 or more) arranged in a first direction, each of the first to n-th blocks including a first memory cell, a first conductive line extending in the first direction, and shared by the first to n-th blocks, first to n-th current amplifiers corresponding to the first to n-th blocks, the i-th current amplifier (i is one of 1 to n) including an input terminal and an output terminal, the input terminal of the i-th current amplifier being electrically connected to the first memory cell in the i-th block, the output terminal of the i-th current amplifier being electrically connected to the first conductive line, and a sense amplifier electrically connected to the first conductive line.

    Abstract translation: 根据一个实施例，半导体存储器包括第一块阵列，其包括以第一方向布置的第一至第n块（n为2或更多的自然数），第一至第n块中的每一个包括第一存储器 第一导电线，其在第一方向上延伸，并且由第一至第n块共享，第一至第n电流放大器对应于第一至第n块，第i电流放大器（i为一 1至n）包括输入端和输出端，第i个电流放大器的输入端电连接到第i个块中的第一个存储单元，第i个电流放大器的输出端为 电连接到第一导线，以及读出放大器，电连接到第一导线。

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