公开(公告)号：US20190066749A1

公开(公告)日：2019-02-28

申请号：US16177186

申请日：2018-10-31

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroaki YODA ,  Naoharu SHIMOMURA ,  Yoshiaki SAITO ,  Yuichi OHSAWA ,  Keiko ABE

IPC: G11C11/16

Abstract: A magnetic memory includes: first to third terminals; a conductive layer including first to fifth regions, the first region being electrically connected to the first terminal, the fifth region being electrically connected to the second terminal, and the third region being electrically connected to the third terminal; a first magnetoresistive element including a first magnetic layer, a second magnetic layer disposed between the second region and the first magnetic layer, and a first nonmagnetic layer disposed between the first and the second magnetic layer; a second magnetoresistive element including a third magnetic layer, a fourth magnetic layer disposed between the fourth region and the third magnetic layer, and a second nonmagnetic layer disposed between the third and the fourth magnetic layer; and a circuit flowing a write current between the first and the second terminal and between the second and the third terminal in a write operation.

公开(公告)号：US20160276031A1

公开(公告)日：2016-09-22

申请号：US15067708

申请日：2016-03-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Keiko ABE ,  Shinobu FUJITA

IPC: G11C14/00

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/412

Abstract: A storage device according to an embodiment includes: first and second magnetic elements each including: a reference layer connected to a third terminal; a first magnetic layer including first through third magnetic regions; a nonmagnetic layer; a second magnetic layer connected to a first terminal and the first magnetic region; and a third magnetic layer connected to a second terminal and the third magnetic region; a first inverter including a p-channel first transistor, an n-channel second transistor, a first input terminal connected to the second terminal of the second magnetic element, and a first output terminal connected to the first terminal of the first magnetic element; and a second inverter including a p-channel third transistor, an n-channel fourth transistor, a second input terminal connected to the second terminal of the first magnetic element, and a second output terminal connected to the first terminal of the second magnetic element.

Abstract translation: 根据实施例的存储装置包括：第一和第二磁性元件，每个包括：连接到第三端子的参考层; 包括第一至第三磁性区域的第一磁性层; 非磁性层; 连接到第一端子和第一磁性区域的第二磁性层; 以及连接到第二端子和第三磁性区域的第三磁性层; 第一反相器，包括p沟道第一晶体管，n沟道第二晶体管，连接到第二磁性元件的第二端子的第一输入端子和连接到第一磁性元件的第一端子的第一输出端子; 以及第二反相器，包括p沟道第三晶体管，n沟道第四晶体管，连接到第一磁性元件的第二端子的第二输入端子和连接到第二磁性元件的第一端子的第二输出端子。

公开(公告)号：US20180277746A1

公开(公告)日：2018-09-27

申请号：US15704867

申请日：2017-09-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiko ABE ,  Kazutaka IKEGAMI ,  Shinobu FUJITA ,  Katsuhiko KOUI ,  Tomoaki INOKUCHI ,  Satoshi SHIROTORI ,  Yuichi OHSAWA ,  Hideyuki SUGIYAMA ,  Hiroaki YODA ,  Naoharu SHIMOMURA ,  Yuuzo KAMIGUCHI

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.

公开(公告)号：US20160019942A1

公开(公告)日：2016-01-21

申请号：US14867674

申请日：2015-09-28

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hiroki NOGUCHI ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Shinobu FUJITA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.

公开(公告)号：US20170047106A1

公开(公告)日：2017-02-16

申请号：US15232956

申请日：2016-08-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi TAKAYA ,  Hiroki NOGUCHI ,  Keiko ABE ,  Shinobu FUJITA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0069 ,  G11C2013/0071

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being connected to the second terminal, and a first driver electrically connected to the control terminal, applying a first potential to the control terminal in a first write operation, and applying a second potential larger than the first potential to the control terminal in a second write operation.

Abstract translation: 根据一个实施例，非易失性半导体存储器包括具有第一和第二端子的电阻变化元件，具有第三和第四端子的晶体管和控制端子，第三端子连接到第二端子，第一驱动器电连接到 所述控制终端在第一写入操作中向所述控制终端施加第一电位，并且在第二写入操作中将大于所述第一电位的第二电位施加到所述控制终端。

公开(公告)号：US20180081570A1

公开(公告)日：2018-03-22

申请号：US15456209

申请日：2017-03-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiko ABE ,  Hiroki NOGUCHI ,  Susumu TAKEDA ,  Kumiko NOMURA ,  Shinobu FUJITA

IPC: G06F3/06 ,  G11C11/406 ,  G06F11/16

Abstract: A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.

公开(公告)号：US20160188429A1

公开(公告)日：2016-06-30

申请号：US15059702

申请日：2016-03-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroki NOGUCHI ,  Shinobu FUJITA ,  Keiko ABE

IPC: G06F11/20 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F11/2069 ,  G06F11/1004 ,  G06F11/1064 ,  G06F11/1068 ,  G06F12/0802 ,  G06F12/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory control circuit has an error determination circuitry to determine whether an error-bit number is larger than a predetermined threshold value set based on a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that an error is contained in data read for verification of data written to the first memory or in data read from the first memory, and an access controller to control access to a second memory having an access priority lower than the first memory when it is determined that the error-bit number is larger than the threshold value, and to control access to the first memory without accessing the second memory when it is determined that the error-bit number is equal to or less than the threshold value.

Abstract translation: 存储器控制电路具有错误确定电路，用于根据由误差校正电路校正的最大错误位数来确定错误位数是否大于设定的预定阈值，当错误检测电路被错误检测器检测到时， 用于对写入第一存储器的数据或从第一存储器读取的数据进行验证的数据读取中包含错误;以及访问控制器，当确定存取控制器的访问优先级低于第一存储器时，控制对第二存储器的访问 错误位数大于阈值，并且当确定错误位数等于或小于阈值时，控制对第一存储器的访问而不访问第二存储器。

公开(公告)号：US20130322161A1

公开(公告)日：2013-12-05

申请号：US13772815

申请日：2013-02-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroki NOGUCHI ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Shinobu FUJITA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.

Abstract translation: 根据一个实施例，磁性随机存取存储器包括用于向第一和第二磁阻元件写入互补数据的写入电路，以及读取电路以从第一和第二磁阻元件读取互补数据。 控制电路被配置为在将第一和第二位线设置为第一电位之后将第一和第二位线改变为浮置状态，并且将浮动状态下的第一位线的电位根据 根据第二磁阻元件的电阻值将第一磁阻元件的电阻值和浮置状态下的第二位线的电位设置为第二值，将第二磁阻元件的电阻值设定为比第一电位高的第二电位 。

公开(公告)号：US20130246818A1

公开(公告)日：2013-09-19

申请号：US13772518

申请日：2013-02-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kumiko NOMURA ,  Shinobu FUJITA ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Hiroki NOGUCHI

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.

Abstract translation: 根据实施例，高速缓存设备包括高速缓冲存储器，访问控制器和功率控制器。 高速缓冲存储器分别包括与多个方式相关联的多个存储区域。 访问控制器控制对存储区域的访问。 功率控制器单独地控制提供给每个存储器区域的功率，使得提供给在预定时间内未被访问的存储区域的功率是低于使得存储区域能够操作的操作功率的待机功率。 功率控制器控制提供给存储区域的功率，使得对于很可能被访问的存储区域的待机功率具有比不太可能被访问的存储区域的待机功率值更接近操作功率的值 。