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    CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM
    1.
    发明申请
    CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM 有权
    缓存记忆系统和处理器系统

    公开(公告)号：US20160357683A1

    公开(公告)日：2016-12-08

    申请号：US15243196

    申请日：2016-08-22

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Susumu TAKEDA ,  Shinobu FUJITA

    IPC: G06F12/0895 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/0897

    CPC classification number: G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/271 ,  G06F2212/507

    Abstract: A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an address of data stored in the data cache, and a first address conversion information storage to store entry information that includes address conversion information for virtual addresses issued by a processor to physical addresses and cache presence information that indicates whether data corresponding to the converted physical address is stored in a specific cache memory of at least one layer among the cache memories,

    Abstract translation: 高速缓冲存储器系统包括至少一层的高速缓存存储器，高速缓存存储器中的至少一个具有存储数据的数据高速缓存和用于存储存储在数据高速缓存中的数据的地址的标签，以及第一地址转换信息存储器 将包括处理器发出的虚拟地址的地址转换信息存储到物理地址的存储条目信息和指示与转换的物理地址相对应的数据是否存储在高速缓冲存储器中的至少一层的特定高速缓冲存储器中的高速缓存存在信息，

    Memory Control Circuit and Storage Device
    2.
    发明申请
    Memory Control Circuit and Storage Device 审中-公开
    存储控制电路和存储设备

    公开(公告)号：US20170004095A1

    公开(公告)日：2017-01-05

    申请号：US15266495

    申请日：2016-09-15

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Susumu TAKEDA ,  Shinobu Fujita

    IPC: G06F12/14 ,  G06F3/06

    CPC classification number: G06F12/1425 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F13/1657 ,  G06F13/1684 ,  G06F2212/1052

    Abstract: A memory control circuit has a memory controller that performs access control for a first memory accessed by a first data amount and access control for a second memory of a memory layer equal to the first memory at a read speed lower than a read speed of the first memory by a second data amount larger than the first data amount.

    Abstract translation: 存储器控制电路具有存储器控制器，其以低于第一数据量的读取速度的读取速度，对与第一存储器等于第一存储器的存储器层的第二存储器执行对第一存储器访问的第一存储器的访问控制， 存储器大于第一数据量的第二数据量。

    MEMORY SYSTEM
    3.
    发明申请
    MEMORY SYSTEM 有权
    记忆系统

    公开(公告)号：US20160267008A1

    公开(公告)日：2016-09-15

    申请号：US15067658

    申请日：2016-03-11

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Susumu TAKEDA

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0246 ,  G06F2212/6012 ,  Y02D10/13

    Abstract: A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.

    Abstract translation: 存储器系统具有包括易失性存储器的第一高速缓存存储器，包括具有比易失性存储器的访问速度慢的访​​问速度的非易失性存储器的第二高速缓存存储器，以及重配置控制电路，用于在使用第二 高速缓冲存储器作为比第一高速缓冲存储器低层的缓存存储器，以及第二模式，其将第一高速缓冲存储器和第二高速缓存存储器用作相同存储器层中的高速缓冲存储器。

    MEMORY SYSTEM
    5.
    发明申请
    MEMORY SYSTEM 审中-公开
    记忆系统

    公开(公告)号：US20160275017A1

    公开(公告)日：2016-09-22

    申请号：US15067558

    申请日：2016-03-11

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Susumu TAKEDA

    IPC: G06F12/10

    CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F12/1027 ,  G06F2212/608 ,  G06F2212/68 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address, and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.

    Abstract translation: 存储器系统具有用作要以比主存储器更高的速度访问的第一高速缓冲存储器的非易失性存储器，第一转换后备缓冲器，其将指示将由处理器发出的虚拟地址的转换的地址转换信息存储到 物理地址和第一控制电路，其在断电期间将存储在第一翻译后备缓冲器中的地址转换信息存储在非易失性存储器中。

    INFORMATION PROCESSING DEVICE, MAGNETIC RECORDING AND REPRODUCING DEVICE, AND MAGNETIC RECORDING AND REPRODUCING SYSTEM
    6.
    发明公开
    INFORMATION PROCESSING DEVICE, MAGNETIC RECORDING AND REPRODUCING DEVICE, AND MAGNETIC RECORDING AND REPRODUCING SYSTEM 审中-公开

    公开(公告)号：US20230298619A1

    公开(公告)日：2023-09-21

    申请号：US17822753

    申请日：2022-08-26

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Susumu TAKEDA ,  Kenichiro YAMADA

    IPC: G11B5/012 ,  G11B5/127

    CPC classification number: G11B5/012 ,  G11B5/127

    Abstract: According to one embodiment, an information processing device includes an acquisition part, and a processor. The acquisition part is configured to acquire a reproduction signal obtained from a recording part. The recording part includes a recording medium. The reproduction signal includes a first signal corresponding to information recorded in the recording medium. The processor is configured to derive a first output and a second output. The first output is obtained by first information being processed by a first processing model. The first information includes the first signal. The second output is obtained by the first information being processed by a second processing model. The processor is configured to output a result of processing the first information based on a third output. The third output is obtained based on the first output, the second output, and the first information.

    INFORMATION PROCESSING METHOD, INFORMATION PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM
    8.
    发明申请
    INFORMATION PROCESSING METHOD, INFORMATION PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM 有权
    信息处理方法，信息处理装置和非终端计算机可读介质

    公开(公告)号：US20160154589A1

    公开(公告)日：2016-06-02

    申请号：US15014673

    申请日：2016-02-03

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Susumu TAKEDA ,  Shinobu Fujita

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0611 ,  G06F3/0631 ,  G06F3/0683 ,  G06F11/3419 ,  G06F11/3466 ,  G06F12/08 ,  G06F12/0897 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/1024

    Abstract: According to one embodiment, an information processing method including: detecting by a time information acquiring unit a start and an end of an access of a memory access unit to a target memory, the access of the memory access unit being due to instructions of an instruction issuer, and acquiring by the time information acquiring unit a memory access time being a time from the start of the access till the end of the access; calculating by a computation amount acquiring unit, based on the instructions of the instruction issuer, a computation amount of a computing unit from the start of the access till the end of the access; and evaluating by an evaluation unit, based on the memory access time and the computation amount, computing performance of the computing unit from the start of the access till the end of the access.

    Abstract translation: 根据一个实施例，一种信息处理方法，包括：由时间信息获取单元检测存储器访问单元对目标存储器的访问的开始和结束，存储器访问单元的访问是由于指令的指令 并且由时间信息获取单元获取存储器访问时间是从访问开始直到访问结束的时间; 由计算量获取单元基于指令发出者的指令，计算单元从访问开始到访问结束的计算量; 并且由评估单元基于存储器访问时间和计算量来评估计算单元从访问开始直到访问结束的计算性能。

    MAGNETIC MEMORY DEVICE
    9.
    发明申请
    MAGNETIC MEMORY DEVICE 审中-公开

    公开(公告)号：US20200279596A1

    公开(公告)日：2020-09-03

    申请号：US16741246

    申请日：2020-01-13

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Tomoaki INOKUCHI ,  Katsuhiko KOUI ,  Naoharu SHIMOMURA ,  Hideyuki SUGIYAMA ,  Kazutaka IKEGAMI ,  Susumu TAKEDA ,  Satoshi TAKAYA ,  Shinobu FUJITA ,  Hiroaki YODA

    IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

    MEMORY SYSTEM AND PROCESSOR SYSTEM
    10.
    发明申请
    MEMORY SYSTEM AND PROCESSOR SYSTEM 审中-公开

    公开(公告)号：US20180081570A1

    公开(公告)日：2018-03-22

    申请号：US15456209

    申请日：2017-03-10

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Keiko ABE ,  Hiroki NOGUCHI ,  Susumu TAKEDA ,  Kumiko NOMURA ,  Shinobu FUJITA

    IPC: G06F3/06 ,  G11C11/406 ,  G06F11/16

    Abstract: A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.

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