公开(公告)号：US09837327B2

公开(公告)日：2017-12-05

申请号：US15070303

申请日：2016-03-15

申请人： Freescale Semiconductor, Inc.

发明人： Lakshminarayan Viswanathan

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04 ,  H01L29/40 ,  H01L23/047 ,  H01L23/00 ,  H01L23/057 ,  H01L23/31 ,  H01L23/14 ,  H01L23/367 ,  H01L21/50 ,  H01L23/492 ,  H01L23/498 ,  H01L25/065 ,  H01L21/288 ,  H01L21/48

CPC分类号： H01L23/047 ,  H01L21/288 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/50 ,  H01L23/057 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/4924 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/2731 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0461 ,  H01L2924/0469 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/16152 ,  H01L2924/16598 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

公开(公告)号：US20170278763A1

公开(公告)日：2017-09-28

申请号：US15079276

申请日：2016-03-24

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Li LI ,  Jaynal A. MOLLA ,  Lakshminarayan VISWANATHAN

IPC分类号： H01L23/047 ,  H01L23/373 ,  H01L21/50 ,  H01L21/56 ,  H01L21/52

CPC分类号： H01L23/047 ,  H01L21/50 ,  H01L21/52 ,  H01L21/566 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2021/60277 ,  H01L2021/603 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29393 ,  H01L2224/29399 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8384 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00

摘要： A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

公开(公告)号：US20170125316A1

公开(公告)日：2017-05-04

申请号：US15165084

申请日：2016-05-26

申请人： Mitsubishi Electric Corporation

发明人： Hiroaki ICHINOHE ,  Tatsuto NISHIHARA ,  Yuji IWAI

IPC分类号： H01L23/10 ,  H01L23/66 ,  H01L23/36 ,  H01L23/552 ,  H01L23/047

CPC分类号： H01L23/10 ,  H01L23/047 ,  H01L23/36 ,  H01L23/552 ,  H01L23/66 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6644 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15151 ,  H01L2924/16195 ,  H01L2924/162 ,  H01L2924/163 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

摘要： A semiconductor device according to the present invention includes a mounting section provided with a chip mounting region for mounting a semiconductor chip, a frame provided in the mounting section so as to surround the chip mounting region, a cap disposed in contact with the frame so as to cover a space surrounded by the chip mounting region and the frame and a joint that joins the frame and the cap outside a contact surface between the frame and the cap.

公开(公告)号：US20170077069A1

公开(公告)日：2017-03-16

申请号：US15211421

申请日：2016-07-15

申请人： Renesas Electronics Corporation

发明人： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA

IPC分类号： H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L23/29 ,  H01L23/495 ,  H01L21/48 ,  H01L23/047 ,  H01L23/498

CPC分类号： H01L24/73 ,  H01L21/4853 ,  H01L23/047 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/92247 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0206 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.

摘要翻译： 半导体器件的可靠性得到改善。 在管芯焊盘上安装第一和第二半导体芯片。 第一和第二半导体芯片和芯片焊盘的一部分被密封在密封部分中。 第一半导体芯片包括功率晶体管。 第二半导体芯片控制第一半导体芯片。 安装第一半导体芯片的芯片焊盘部分的厚度小于安装第二半导体芯片的芯片焊盘部分的厚度。

公开(公告)号：US20160293508A1

公开(公告)日：2016-10-06

申请号：US15070308

申请日：2016-03-15

申请人： Freescale Semiconductor, Inc.

发明人： Lakshminarayan Viswanathan

IPC分类号： H01L23/047 ,  H01L23/498 ,  H01L23/367 ,  H01L23/14 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/492

CPC分类号： H01L23/047 ,  H01L21/288 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/50 ,  H01L23/057 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/4924 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/2731 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0461 ,  H01L2924/0469 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/16152 ,  H01L2924/16598 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

摘要翻译： 提供了结合使用银耦合的陶瓷，有机和金属材料的组合的半导体器件封装。 银在加压和低温下以微粒的形式施加。 应用后，银形成具有典型的银熔点的固体，因此成品封装可承受明显高于制造温度的温度。 此外，由于银是各种组合材料之间的界面材料，所以陶瓷，有机和金属组分之间的不同材料性质（如热膨胀系数）的影响由于低粘结温度和 银。

公开(公告)号：US09449893B2

公开(公告)日：2016-09-20

申请号：US13607872

申请日：2012-09-10

申请人： Shinsuke Oota

发明人： Shinsuke Oota

IPC分类号： H01L29/10 ,  H01L23/36 ,  H01L23/047 ,  H01L23/433 ,  H01L23/495 ,  H01L25/11

CPC分类号： H01L23/36 ,  H01L23/047 ,  H01L23/4334 ,  H01L23/49562 ,  H01L25/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor module includes a semiconductor chip having a switching function, a resin portion that covers the chip, terminals, and a heat dissipation portion. The resin portion includes first and second surfaces, which are opposed to each other and expand generally parallel to an imaginary plane; and a substrate is located on a first surface-side of the resin portion. The terminals project from the resin portion in a direction of the imaginary plane and are soldered onto the substrate. The heat dissipation portion is disposed on a second surface-side of the resin portion to release heat generated in the chip. One of the terminals is connected to the heat dissipation portion such that heat is transmitted from the one of the terminals to the heat dissipation portion.

摘要翻译： 半导体模块包括具有开关功能的半导体芯片，覆盖芯片的树脂部分，端子和散热部分。 树脂部分包括第一和第二表面，它们彼此相对并且大致平行于假想平面膨胀; 并且衬底位于树脂部分的第一表面侧上。 端子从假想平面的方向从树脂部分突出并焊接到基板上。 散热部设置在树脂部的第二表面侧，以释放在芯片中产生的热量。 其中一个端子连接到散热部分，使得热量从一个端子传递到散热部分。

公开(公告)号：US09438184B2

公开(公告)日：2016-09-06

申请号：US14317572

申请日：2014-06-27

申请人： Jeffrey K. Jones ,  Basim H. Noori ,  Michael E. Watts

发明人： Jeffrey K. Jones ,  Basim H. Noori ,  Michael E. Watts

IPC分类号： H01L21/8242 ,  H01L29/86 ,  H01L29/06 ,  H03F3/21 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H03F1/56 ,  H01L23/047 ,  H03F3/195 ,  H03F3/193

CPC分类号： H03F3/21 ,  H01G4/385 ,  H01G4/40 ,  H01L23/047 ,  H01L23/481 ,  H01L23/488 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/19104 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： An embodiment of an integrated passive device (IPD) assembly includes a first capacitor formed over a semiconductor substrate, where the first capacitor includes a first capacitor electrode, a second capacitor electrode, and dielectric material that electrically insulates the first capacitor electrode from the second capacitor electrode. The IPD assembly also includes a first contact pad exposed at a top surface of the IPD assembly and electrically coupled to the second capacitor electrode, and a second contact pad exposed at the top surface of the IPD. A second capacitor is coupled to the top surface of the IPD, and includes a first terminal electrically coupled to the first contact pad, and a second terminal electrically coupled to the second contact pad. The IPD assembly may be included in a packaged RF device, forming portions of an output impedance matching circuit and an envelope frequency termination circuit.

摘要翻译： 集成无源器件（IPD）组件的实施例包括形成在半导体衬底上的第一电容器，其中第一电容器包括第一电容器电极，第二电容器电极和将第一电容器电极与第二电容器电绝缘的电介质材料 电极。 IPD组件还包括暴露在IPD组件的顶表面处并电耦合到第二电容器电极的第一接触焊盘和暴露在IPD的顶表面处的第二接触焊盘。 第二电容器耦合到IPD的顶表面，并且包括电耦合到第一接触焊盘的第一端子和电耦合到第二接触焊盘的第二端子。 IPD组件可以包括在封装的RF器件中，形成输出阻抗匹配电路的一部分和封装频率终止电路。

公开(公告)号：US09401342B2

公开(公告)日：2016-07-26

申请号：US13929688

申请日：2013-06-27

申请人： Shun Meen Kuo ,  Margaret Szymanowski ,  Paul Hart

发明人： Shun Meen Kuo ,  Margaret Szymanowski ,  Paul Hart

IPC分类号： H03F3/68 ,  H03F3/195 ,  H01L23/00 ,  H03F1/02 ,  H03F1/56 ,  H03F3/24 ,  H01L23/047 ,  H01L23/552 ,  H01L23/66 ,  H01L23/24

CPC分类号： H01L24/85 ,  H01L23/047 ,  H01L23/24 ,  H01L23/552 ,  H01L23/66 ,  H01L24/45 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6661 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/0288 ,  H03F1/56 ,  H03F3/195 ,  H03F3/245 ,  H01L2924/00 ,  H01L2224/05599

摘要： A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

摘要翻译： 提出了一种用于包装件的系统和方法，其包括用于减少耦合的线接合壁。 所述封装包括衬底和所述衬底上的第一电路。 第一电路包括第一电气设备，第二电气设备和互连第一电气设备和第二电气设备的第一引线键合阵列。 所述封装包括与所述第一电路相邻的所述衬底上的第二电路，所述第二电路包括互连第三电气设备和第四电气设备的第二引线接合阵列。 该封装包括引线接合壁，其包括在第一电路和第二电路之间的衬底上的多个引线键合。 引线接合壁被配置为在第一电路和第二电路中的至少一个的操作期间减小第一电路和第二电路之间的电磁耦合。

公开(公告)号：US09397033B2

公开(公告)日：2016-07-19

申请号：US14724556

申请日：2015-05-28

申请人： Sumitomo Electric Industries, Ltd.

发明人： Masaki Furumai

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/047 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L23/047 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： The semiconductor device in accordance with one mode comprises a semiconductor chip; a chip mounting substrate on which the semiconductor chip is mounted; a chip container that is provided on the chip mounting substrate and contains the semiconductor chip; and a seal part that seals the chip container containing the semiconductor chip and the chip mounting substrate. The chip container has a frame part surrounding a periphery of the semiconductor chip. The height of the frame part is greater than that of the semiconductor chip. The inside of the frame part in the chip container is provided with a chip coating material that protects the semiconductor chip.

摘要翻译： 根据一种模式的半导体器件包括半导体芯片; 安装半导体芯片的芯片安装基板; 芯片容器，设置在芯片安装基板上并且包含半导体芯片; 以及密封包含半导体芯片的芯片容器和芯片安装基板的密封部。 芯片容器具有围绕半导体芯片周边的框架部分。 框架部分的高度大于半导体芯片的高度。 芯片容器中的框架部分的内部设置有保护半导体芯片的芯片涂覆材料。

公开(公告)号：US20160172318A1

公开(公告)日：2016-06-16

申请号：US15050176

申请日：2016-02-22

申请人： Freescale Semiconductor, Inc.

发明人： Lakshminarayan Viswanathan ,  Jeffrey K. Jones ,  Scott D. Marshall

IPC分类号： H01L23/66 ,  H01L23/495 ,  H01L23/047

CPC分类号： H01L23/66 ,  H01L23/047 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

摘要： Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices.

摘要翻译： 半导体器件（例如，RF器件）的实施例包括衬底，隔离结构，有源器件，引线和电路。 隔离结构耦合到衬底，并且包括开口。 有源器件区域由通过开口暴露的衬底表面的一部分限定。 有源器件耦合到有源器件区域内的衬底表面。 电路电耦合在有源器件和引线之间。 电路包括位于有源器件区域外的一个或多个元件（例如，物理耦合到隔离结构和/或在引线下方）。 位于有源器件区域之外的元件可以包括封装端接电路和/或阻抗匹配电路的元件。 实施例还包括制造这种半导体器件的方法。