公开(公告)号：US20180026018A1

公开(公告)日：2018-01-25

申请号：US15393083

申请日：2016-12-28

申请人： Invensas Corporation

发明人： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC分类号： H01L25/10 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

摘要： Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.

公开(公告)号：US09875911B2

公开(公告)日：2018-01-23

申请号：US12714190

申请日：2010-02-26

申请人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

发明人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

IPC分类号： H01L23/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L23/00 ,  H01L23/552

CPC分类号： H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

公开(公告)号：US20180019227A1

公开(公告)日：2018-01-18

申请号：US15210403

申请日：2016-07-14

申请人： GLOBALFOUNDRIES INC.

发明人： Sebastian T. Ventrone ,  Sudeep Mandal

IPC分类号： H01L25/065 ,  G11C15/04 ,  G11C15/06

CPC分类号： H01L25/0657 ,  G11C15/04 ,  G11C15/06 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572

摘要： The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.

公开(公告)号：US20180019221A1

公开(公告)日：2018-01-18

申请号：US15649545

申请日：2017-07-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  Chi-Tsung CHIU

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L23/3135 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2518 ,  H01L2224/32146 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/01022 ,  H01L2924/01029

摘要： A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

公开(公告)号：US20180012880A1

公开(公告)日：2018-01-11

申请号：US15205238

申请日：2016-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Chun YANG ,  Yi-Li HSIAO ,  Tung-Liang SHAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC分类号： H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/30604 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/18161

摘要： Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.

公开(公告)号：US09865569B2

公开(公告)日：2018-01-09

申请号：US15137123

申请日：2016-04-25

申请人： International Business Machines Corporation

发明人： Bing Dang ,  John U. Knickerbocker ,  Yang Liu ,  Yu Luo ,  Steven L. Wright

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L23/50 ,  H01L23/13 ,  H01L21/66 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L22/14 ,  H01L22/20 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11334 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/17104 ,  H01L2224/1712 ,  H01L2224/1751 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06565

摘要： A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint.

公开(公告)号：US20180005989A1

公开(公告)日：2018-01-04

申请号：US15196937

申请日：2016-06-29

申请人： Intel Corporation

发明人： Saikumar Jayaraman ,  John S. Guzek ,  Yidnekachew S. Mekonnen

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/85815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

摘要： Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.

公开(公告)号：US09859256B1

公开(公告)日：2018-01-02

申请号：US15335331

申请日：2016-10-26

申请人： STMICROELECTRONICS S.R.L.

发明人： Federico Giovanni Ziglioli

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/09 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/85345 ,  H01L2224/8584 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568

摘要： An integrated circuit package with improved reliability and methods for creating the same are disclosed. More specifically, integrated circuit packages are created using one or more sacrificial layers that provide support for ink printed wires prior to package processing, but are removed during package processing. Once each of the sacrificial layers is removed, molding compound is placed around each ink printed wire, which may have a substantially rectangular cross section that can vary in dimension along a length of a given wire. While substantially surrounding each wire in and of itself improves reliability, removing non-conductive paste, fillets, or other adhesive materials also minimizes adhesion issues between the molding compound and those materials, which increases the bond of the molding compound to the package and its components. The net result is a more reliable integrated circuit package that is less susceptible to internal cracking and wire damage.

公开(公告)号：US09859193B2

公开(公告)日：2018-01-02

申请号：US15600793

申请日：2017-05-22

申请人： IBIS Innotech Inc.

发明人： Wen-Chun Liu ,  Wei-Jen Lai

IPC分类号： H01L23/495 ,  H01L23/60

CPC分类号： H01L23/49503 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/053 ,  H01L23/481 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/60 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

摘要： A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.

公开(公告)号：US09847324B2

公开(公告)日：2017-12-19

申请号：US14730030

申请日：2015-06-03

申请人： STATS ChipPAC, Ltd.

发明人： Yaojian Lin ,  Kang Chen

IPC分类号： H01L25/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/10 ,  H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/04 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/0613 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/13015 ,  H01L2224/81

摘要： A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.