公开(公告)号：US20180019227A1

公开(公告)日：2018-01-18

申请号：US15210403

申请日：2016-07-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian T. Ventrone ,  Sudeep Mandal

IPC: H01L25/065 ,  G11C15/04 ,  G11C15/06

CPC classification number: H01L25/0657 ,  G11C15/04 ,  G11C15/06 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.

公开(公告)号：US5629889A

公开(公告)日：1997-05-13

申请号：US572483

申请日：1995-12-14

Applicant: Premala Chandra ,  Lev B. Loffe

Inventor： Premala Chandra ,  Lev B. Loffe

IPC: G11C11/44 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00

CPC classification number: G11C29/88 ,  G11C11/44 ,  G11C15/06 ,  Y10S505/832 ,  Y10S505/841

Abstract: A superconducting fault-tolerant programmable read-only memory (SFT-PROM) cell stores information in the phases of superconducting wires in a Josephson array. The information is addressable and retrievable in a fault-tolerant manner due to the non local nature of the information stored. The coding and decoding process is content-addressable and parallel due to the multitude of interconnections, resulting in picosecond data access time. The SFT-PROM cell comprises superposed WRITE/READ arrays and a reset circuit that ensures multiple non-destructive read-out of data.

Abstract translation: 超导容错可编程只读存储器（SFT-PROM）单元在约瑟夫逊阵列中的超导线的相位中存储信息。 由于存储的信息的非本地性质，该信息是可寻址的并且以容错方式可检索。 编码和解码过程是内容寻址和并行的，由于众多的互连，导致皮秒数据访问时间。 SFT-PROM单元包括叠加的写入/读取阵列和复位电路，其确保数据的多个非破坏性读出。

公开(公告)号：US3744038A

公开(公告)日：1973-07-03

申请号：US3744038D

申请日：1971-07-09

Applicant: ROBOTRON VEB K

Inventor： KNEUPEL H ,  STEFFIN B

IPC: G06K9/66 ,  G06N3/063 ,  G11C11/44 ,  G11C15/06 ,  G11C27/00 ,  H03K25/00

CPC classification number: G06K9/66 ,  G06N3/063 ,  G11C11/44 ,  G11C15/06 ,  Y10S505/84

Abstract: A superconducting learning matrix in which the coupling cells at the matrix intersections include a write cryotron controlled by the row lines for activating the storage cells, and a coupling cryotron for coupling the column lines either to the row lines or word recognition lines for reading out of the cell. The storage cells are activated according to a geometric series. The coupling cryotrons may also be controlled by a blocking line, and additional switching cryotrons may be provided for insuring constant current in taught cells. In a further embodiment, a complementary matrix may also be provided.

Abstract translation: 一种超导学习矩阵，其中矩阵交点处的耦合单元包括由用于激活存储单元的行线控制的写入深冷子，以及用于将列线耦合到行线或字识别线用于读出的耦合低温电极 细胞。 存储单元根据几何系列被激活。 耦合低温电极也可以通过阻塞线来控制，并且可以提供额外的开关式低温电极用于确保所教导的电池中的恒定电流。 在另一实施例中，还可以提供互补矩阵。

公开(公告)号：US3460102A

公开(公告)日：1969-08-05

申请号：US3460102D

申请日：1967-04-20

Applicant: SIEMENS AG

Inventor： GOSER KARL ,  KADEREIT HANS-GUNTHER

IPC: G11C15/06 ,  G11B9/02

CPC classification number: G11C15/06 ,  Y10S505/835

公开(公告)号：US3430205A

公开(公告)日：1969-02-25

申请号：US3430205D

申请日：1966-03-24

Applicant: IBM

Inventor： SEEBER ROBERT R ,  LINDOUIST ARWIN B

IPC: G11C11/44 ,  G11C15/06 ,  G11B13/00

CPC classification number: G11C11/44 ,  G11C15/06

公开(公告)号：US3416146A

公开(公告)日：1968-12-10

申请号：US41987664

申请日：1964-12-21

Applicant: GEN ELECTRIC

Inventor： BREMER JOHN W

IPC: G11C15/06

CPC classification number: G11C15/06 ,  Y10S505/839

公开(公告)号：US3312956A

公开(公告)日：1967-04-04

申请号：US24903363

申请日：1963-01-02

Applicant: GEN ELECTRIC

Inventor： WOOD BREMER JOHN ,  DOSS DWIGHT W ,  MCKEEVER BRUCE T

IPC: G11C11/44 ,  G11C15/06

CPC classification number: G11C11/44 ,  G11C15/06 ,  Y10S505/835

公开(公告)号：US3235839A

公开(公告)日：1966-02-15

申请号：US17651962

申请日：1962-03-01

Applicant: BURROUGHS CORP

Inventor： HARVEY ROSENBERG

IPC: G11C15/06

CPC classification number: G11C15/06 ,  Y10S505/835

公开(公告)号：US3229255A

公开(公告)日：1966-01-11

申请号：US85879359

申请日：1959-12-10

Applicant: IBM

Inventor： ANDERSON JOHN L

IPC: G11C11/44 ,  G11C15/06

CPC classification number: G11C15/06 ,  G11C11/44 ,  Y10S505/831

公开(公告)号：US09741419B1

公开(公告)日：2017-08-22

申请号：US15437379

申请日：2017-02-20

Applicant: Microsoft Technology Licensing, LLC

Inventor： William R Reohr ,  Brian R Konigsburg

IPC: G11C11/44 ,  G11C11/16 ,  G11C15/02

CPC classification number: G11C11/1675 ,  G11C11/1673 ,  G11C11/44 ,  G11C15/02 ,  G11C15/04 ,  G11C15/046 ,  G11C15/06

Abstract: A memory system including a content addressable memory having an array of content addressable memory elements including a plurality of rows of content addressable memory elements and a plurality of columns of content addressable memory elements is provided. Each of the content addressable memory elements further includes a first superconducting quantum interference device (SQUID) and a second superconducting quantum interference device (SQUID), where an input bit to each of the content addressable memory elements is compared with: (1) a first state of the first SQUID and (2) a second state of the second SQUID to generate an output signal. The memory system further includes a Josephson magnetic random access memory (JMRAM), coupled to the content addressable memory.