公开(公告)号：US10014410B2

公开(公告)日：2018-07-03

申请号：US15505563

申请日：2014-12-02

申请人： Renesas Electronics Corporation

发明人： Tadashi Yamaguchi

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66 ,  H01L21/285

CPC分类号： H01L29/7845 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A silicide layer on a gate electrode of a MONOS memory is prevented from being disconnected, and a property of a MISFET is improved. As means for that, when a memory cell and a MISFET formed by so-called gate-last process are mixedly mounted, a silicide layer on a source/drain region is formed by a salicide process with relatively high temperature heat treatment, and then, a silicide layer is formed on each of the control gate electrode and the memory gate electrode of the memory cell by a salicide process with relatively low temperature heat treatment.

公开(公告)号：US20180182802A1

公开(公告)日：2018-06-28

申请号：US15849229

申请日：2017-12-20

申请人： CANON KABUSHIKI KAISHA

发明人： Tsutomu Tange ,  Yukinobu Suzuki ,  Aiko Kato ,  Koji Hara ,  Takehito Okabe

IPC分类号： H01L27/146 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L27/14636 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/14612 ,  H01L27/14685 ,  H01L29/0847 ,  H01L29/78

摘要： A semiconductor apparatus includes a silicon layer including first and second semiconductor regions; an insulator film, on the silicon layer, having first and second holes positioned on the first and second semiconductor regions; a first metal portion containing a first metal element in the first hole; a first conductor portion containing a second metal element between the first metal portion and the first semiconductor region; a first silicide region containing the second metal element between the first conductor portion and the first semiconductor region; a second metal portion containing the first metal element in the second hole; a second conductor portion containing the second metal element between the second metal portion and the second semiconductor region; and a second silicide region containing a third metal element between the second conductor portion and the second semiconductor region, wherein the first conductor portion thickness is greater than the second conductor portion thickness.

公开(公告)号：US20180174968A1

公开(公告)日：2018-06-21

申请号：US15824792

申请日：2017-11-28

申请人： D3 Semiconductor LLC

发明人： Thomas E. Harrington, III

IPC分类号： H01L23/535 ,  H01L29/78 ,  H01L21/285 ,  H01L29/739 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L23/532 ,  H01L21/768 ,  H01L29/10

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53266 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7811

摘要： A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.

公开(公告)号：US20180174921A1

公开(公告)日：2018-06-21

申请号：US15843316

申请日：2017-12-15

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei ZHOU

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a substrate, including a first region and a second region; forming a first doped region in the first region of the substrate, the first doped region having first doping ions; forming a second doped region in the second region of the substrate, the second doped region having second dopant ions with a conductivity type opposite to the first doping ions; forming a first metallide on a surface of the first doped region having the first doping ions; and forming a second metallide on a surface of the second doped region having the second doping ions, the second metallide and the first metallide being made of different materials.

公开(公告)号：US20180151410A1

公开(公告)日：2018-05-31

申请号：US15795051

申请日：2017-10-26

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tatsuya USAMI

IPC分类号： H01L21/74 ,  H01L21/308 ,  H01L21/285 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/743 ,  H01L21/28518 ,  H01L21/308 ,  H01L21/76879 ,  H01L29/7816

摘要： To improve the characteristics of a semiconductor device having a substrate contact formed in a deep trench. In a method of forming a plug PSUB in a deep trench DT2 that penetrates an n-type buried layer NBL and reaches a p-type epitaxial layer PEP1, the plug PSUB is formed in the deep trench DT2 after a metal silicide layer SIL1 is formed in the p-type epitaxial layer PEP1. The metal silicide layer SIL1 is formed using a PVD-first metal film (a first metal film formed by PVD). A first barrier metal film BM1 at the bottom of the plug PSUB is a CVD-second metal film (a second metal film formed by CVD). The first metal film is a metal film different from the second metal film.

公开(公告)号：US20180148830A1

公开(公告)日：2018-05-31

申请号：US15573770

申请日：2016-06-24

申请人： TANAKA KIKINZOKU KOGYO K.K. ,  TOKYO INSTITUTE OF TECHNOLOGY

发明人： Shunichiro OHMI ,  Yasushi MASAHIRO

IPC分类号： C23C14/58 ,  C23C14/18 ,  H01L29/45 ,  H01L21/285

CPC分类号： C23C14/5806 ,  C22C5/04 ,  C23C14/18 ,  C23C14/185 ,  C23C14/3414 ,  C23C14/35 ,  C23C14/46 ,  H01L21/28 ,  H01L21/28518 ,  H01L29/417 ,  H01L29/456 ,  H01L29/78

摘要： The present invention relates to a silicide alloy film that is formed on a substrate containing Si, the silicide alloy film including a metal M1 having a work function of 4.6 eV or more and 5.7 eV or less, a metal M2 having a work function of 2.5 eV or less and 4.0 eV or more, and Si, the silicide alloy film having a work function of 4.3 eV or more and 4.9 eV or less. Here, the metal M1 is preferably Pt, Pd, Mo, Ir, W or Ru, and the metal M2 is preferably Hf, La, Er, Ho, Er, Eu, Pr or Sm. The silicide alloy film according to the present invention is a thin-film which has excellent heat-resistance and favorable electrical property.

公开(公告)号：US09985026B2

公开(公告)日：2018-05-29

申请号：US14461061

申请日：2014-08-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/786 ,  H01L29/06 ,  H01L23/485 ,  H01L21/768

CPC分类号： H01L27/092 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L29/0676 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises multiple conductive layers.

公开(公告)号：US09978757B2

公开(公告)日：2018-05-22

申请号：US14837177

申请日：2015-08-27

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/115 ,  H01L23/528 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11517 ,  H01L27/12 ,  H01L49/02 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L27/105 ,  H01L21/108 ,  G11C16/04 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

公开(公告)号：US09972682B2

公开(公告)日：2018-05-15

申请号：US15004756

申请日：2016-01-22

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

发明人： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC分类号： H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

CPC分类号： H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20180130900A1

公开(公告)日：2018-05-10

申请号：US15786366

申请日：2017-10-17

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tatsuya USAMI

IPC分类号： H01L29/786 ,  H01L21/764 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12

CPC分类号： H01L21/762 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0649

摘要： To provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A PVD-metal film (metal film formed by PVD) is used as a first barrier metal film which is a lowermost layer barrier metal film formed in a deep trench penetrating an n type epitaxial layer and a reaching a layer therebelow. Such a configuration makes it possible to stably form a metal silicide layer at a boundary between the PVD-metal film and a silicon layer therebelow (or silicon substrate) and thereby stabilize the contact resistance.