公开(公告)号：US09496181B2

公开(公告)日：2016-11-15

申请号：US14581244

申请日：2014-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7851

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active portion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract translation: 鳍状结构可以包括半导体衬底的表面上的翅片。 每个翅片可以包括靠近半导体衬底的表面的掺杂部分。 鳍状结构还可以包括设置在散热片之间和半导体衬底的表面上的隔离层。 鳍状结构还可以包括在散热片的掺杂部分的侧壁上的凹陷的隔离衬垫。 翅片的无衬里的掺杂部分可以从凹陷的隔离衬垫延伸到隔离层的表面处的翅片的有源部分。 隔离层设置在翅片的无衬里的掺杂部分上。

公开(公告)号：US09478541B2

公开(公告)日：2016-10-25

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap ,  Roawen Chen

IPC: G06F17/50 ,  H01L27/088 ,  G03F7/00 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。

公开(公告)号：US09478490B2

公开(公告)日：2016-10-25

申请号：US14483110

申请日：2014-09-10

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang ,  Jeffrey Junhao Xu

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/00 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract translation: 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US20160247714A1

公开(公告)日：2016-08-25

申请号：US14627653

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/535 ,  G06F17/50 ,  H01L21/311

CPC classification number: H01L21/76802 ,  G03F1/14 ,  G03F7/203 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/7045 ,  G03F7/70466 ,  G06F17/5077 ,  H01L21/31116 ,  H01L23/535

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract translation: 公开了基于电子束（e-beam）的半导体器件特征。 在特定方面，一种方法包括执行第一光刻工艺以在半导体器件上制造第一组切割图案特征。 从特征到有效区域的第一组切割图案特征的每个特征的距离大于或等于阈值距离。 该方法还包括执行电子束（e-beam）工艺以在半导体器件上制造第二切割图案特征。 第二切割图案特征从第二切割图案特征到有效区域的第二距离小于或等于阈值距离。

公开(公告)号：US20160240485A1

公开(公告)日：2016-08-18

申请号：US14622516

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Da Yang ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/02 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/535

Abstract: An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).

Abstract translation: 电子设备包括中间线（MOL）堆叠。 电子器件包括顶部局部互连层和通过第一介电层将顶部局部互连层耦合到半导体器件的栅极的接触。 电子设备还包括在接触件和第一介电层之间的一个或多个隔离壁，其中一个或多个隔离壁包括氮化铝（AlN）。

公开(公告)号：US09343357B2

公开(公告)日：2016-05-17

申请号：US14274099

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Choh Fei Yeap

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

Abstract translation: 半导体器件包括具有将第一互连层耦合到沟槽的通孔的管芯。 半导体器件还包括在沟槽的侧壁和相邻表面上以及在通孔的侧壁上的阻挡层。 半导体器件在第一互连层的表面上具有掺杂的导电层。 掺杂导电层在通孔的侧壁之间延伸。 半导体器件还包括在通孔和沟槽中的阻挡层上的导电材料。 导电材料位于设置在第一互连层表面上的掺杂导电层上。

公开(公告)号：US09306066B2

公开(公告)日：2016-04-05

申请号：US14281660

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Choh Fei Yeap

IPC: H01L27/01 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/02164 ,  H01L21/02238 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.

Abstract translation: 半导体鳍片在基板上，并且在平行于基板的纵向方向上延伸。 翅片在垂直方向上突出到底板上方翅片高度的翅片顶部。 嵌入式翅片应力元件嵌入翅片。 翅片应力元件构造成促使平行于垂直方向的翅片内的垂直压缩力。 可选地，半导体材料包括硅，并且嵌入式翅片应力元件包括二氧化硅。

公开(公告)号：US09165929B2

公开(公告)日：2015-10-20

申请号：US14322207

申请日：2014-07-02

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161

Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.

Abstract translation: 互补翅片场效应晶体管（FinFET）包括具有p沟道鳍片的p型器件。 p沟道鳍可以包括相对于半导体衬底而晶格失配的第一材料。 第一种材料可能具有压缩应变。 FinFET器件还包括具有再通道鳍片的n型器件。 n沟道翅片可以包括具有相对于半导体衬底的晶格失配的拉伸应变的第二材料。 p型器件和n型器件配合形成互补FinFET器件。

公开(公告)号：US20150270134A1

公开(公告)日：2015-09-24

申请号：US14284958

申请日：2014-05-22

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/285 ,  H01L29/66 ,  C23C14/54 ,  C23C16/52 ,  C23C16/46 ,  C23C14/24 ,  H01L21/324 ,  H01L29/45

CPC classification number: H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

Abstract translation: 一种方法包括通过化学气相沉积（CVD）在n型金属氧化物半导体（NMOS）器件的源极/漏极区域和p型MOS（PMOS）器件的源极/漏极区域上形成第一金属层， 或非能量物理气相沉积（PVD）。 该方法还包括在形成第一金属层之后在第一金属层上选择性地执行快速热退火（RTA）工艺。

公开(公告)号：US20150262875A1

公开(公告)日：2015-09-17

申请号：US14471086

申请日：2014-08-28

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76879 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76885

Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.

Abstract translation: 一种方法包括形成包括衬底，氧化物层和第一低k层的电子器件结构。 该方法还包括通过图案化氧化物层来形成开口，用导电材料填充开口以在开口内形成导电结构，以及使用第一低k层作为蚀刻停止层去除氧化物层。 导电结构接触第一低k层。 去除氧化物层包括相对于氧化物层执行化学气相蚀刻工艺以形成蚀刻副产物并除去蚀刻副产物。 该方法包括使用使第二低k层限定一个或多个空腔的沉积工艺形成第二低k层。 每个空腔限定在第一导电结构和相邻的导电结构之间，第一和第二导电结构之间具有小于阈值距离的间隔。