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    THREE-DIMENSIONAL (3D) CARBON NANOTUBE GATE METAL OXIDE (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETS), AND RELATED FABRICATION PROCESSES
    62.
    发明申请
    THREE-DIMENSIONAL (3D) CARBON NANOTUBE GATE METAL OXIDE (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETS), AND RELATED FABRICATION PROCESSES 审中-公开

    公开(公告)号：US20200091448A1

    公开(公告)日：2020-03-19

    申请号：US16130457

    申请日：2018-09-13

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

    IPC: H01L51/05 ,  H01L51/00 ,  H01L27/06

    Abstract: Three-dimensional (3D) carbon nanotube gate field-effect transistors (FETs), that use carbon nanotubes to form a gate, and related fabrication methods are disclosed. A carbon nanotube gate can provide for greater channel control and enlarge the effective channel width of the 3D FET, thus increasing drive strength. Carbon nanotubes have lower surface scatter and have been found to be diffusive such that resistance dominates carrier transport, thus causing higher carrier mobility. A 3D FET can be provided that includes a gate formed from carbon nanotube(s) disposed adjacent to a semiconductor channel formed from a carbon nanotube(s). A dual-gate FET can be provided employing a carbon nanotube gate(s) comprising a front and back carbon nanotube with a semiconductor channel formed therebetween.

    Variable thickness gate oxide transcap
    63.
    发明授权
    Variable thickness gate oxide transcap 有权

    公开(公告)号：US10580908B2

    公开(公告)日：2020-03-03

    申请号：US15947667

    申请日：2018-04-06

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

    IPC: H01L29/93 ,  H01L27/08 ,  H01L29/06 ,  H01G7/06 ,  H01L29/739 ,  H01L29/94

    Abstract: Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

    SRAM read preferred bit cell with write assist circuit
    68.
    发明授权
    SRAM read preferred bit cell with write assist circuit 有权
    SRAM通过写辅助电路读取优先位单元

    公开(公告)号：US09583178B2

    公开(公告)日：2017-02-28

    申请号：US13741869

    申请日：2013-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

    Abstract translation: 静态存储单元的方法和装置。 静态存储单元可以包括第一栅极晶体管，其包括第一背栅极节点和包括第二后栅极节点的第二栅极晶体管。 静态存储单元可以包括包括第三后栅极节点的第一下拉晶体管和包括第四背栅极节点的第二下拉晶体管。 第一下拉晶体管的源节点，第二下拉晶体管的源节点以及第一，第二，第三和第四后门节点彼此电耦合以形成公共节点。

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