公开(公告)号：US10396188B1

公开(公告)日：2019-08-27

申请号：US15962859

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li

IPC: H01L29/66 ,  H01L29/737 ,  H01L27/082 ,  H01L29/205 ,  H01L29/06

Abstract: A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter may be smaller than 100 nanometers, which is suitable for high speed applications.

公开(公告)号：US20190019538A1

公开(公告)日：2019-01-17

申请号：US15817441

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C7/12 ,  G11C8/08 ,  G06N3/08

CPC classification number: G11C5/02 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/161 ,  G11C11/223 ,  G11C11/54 ,  G11C13/0002 ,  G11C16/0483 ,  H03K19/18

Abstract: Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

公开(公告)号：US20200235098A1

公开(公告)日：2020-07-23

申请号：US16255008

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L21/8238

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis andY-axis dimensions of the horizontal footprint are reduced.

公开(公告)号：US20190288662A1

公开(公告)日：2019-09-19

申请号：US15922013

申请日：2018-03-15

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Periannan Chidambaram

IPC: H03H9/02 ,  H03H9/72 ,  H03H9/13 ,  H03H9/145 ,  H03H9/64

Abstract: A surface acoustic wave (SAW) device comprises a substrate and composite electrodes. The composite electrodes comprise a metal layer and a graphene layer. The SAW device may be used to satisfy requirements for the fifth generation (5G) mobile communication.

公开(公告)号：US20190088660A1

公开(公告)日：2019-03-21

申请号：US15708913

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/16 ,  H01L21/762 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G11C11/419

Abstract: Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

公开(公告)号：US10205018B1

公开(公告)日：2019-02-12

申请号：US15676494

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L27/092 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel disposed above the substrate, and a first dielectric layer disposed adjacent to a first side of the channel. The semiconductor device may also include a first non-insulative region disposed between the first dielectric layer and the substrate, and a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers. In certain aspects, a second non-insulative region may be disposed above the second dielectric layer, and a third non-insulative region may be disposed adjacent to a third side of the channel.

公开(公告)号：US10084074B1

公开(公告)日：2018-09-25

申请号：US15643815

申请日：2017-07-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/423 ,  H01L29/778 ,  H01L29/66

Abstract: A compound semiconductor transistor may include a channel layer. The compound semiconductor transistor may also include a dielectric layer on the channel layer. The compound semiconductor transistor may further include a gate. The gate may include a vertical base portion through the dielectric layer and electrically contacting the channel layer. The gate may also include a head portion on the dielectric layer and electrically coupled to the vertical base portion of the gate.

公开(公告)号：US10026731B1

公开(公告)日：2018-07-17

申请号：US15488108

申请日：2017-04-14

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

IPC: H01L29/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/737

Abstract: A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on the compound semiconductor substrate, a first dielectric layer on the collector contact layer, a conductive electrode layer on the first dielectric layer, and a second dielectric layer on the conductive electrode layer. The MIM capacitor includes a first conductive interconnect on the second dielectric layer, a third dielectric layer on the first conductive interconnect, and a second conductive interconnect on the third dielectric layer. A first capacitive component includes the collector contact layer, the conductive electrode layer, and the first dielectric layer. A second capacitive component includes the first conductive interconnect, the conductive electrode layer and the second dielectric layer. A third capacitive component includes the second conductive interconnect, the first conductive interconnect, and the third dielectric layer. The first, second, and third capacitive components are arranged in parallel with each other.

公开(公告)号：US11515406B2

公开(公告)日：2022-11-29

申请号：US16379904

申请日：2019-04-10

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/737 ,  H01L29/40 ,  H01L29/66 ,  H03F3/19

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

公开(公告)号：US10734384B1

公开(公告)日：2020-08-04

申请号：US16255008

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.