公开(公告)号：US09608107B2

公开(公告)日：2017-03-28

申请号：US14192097

申请日：2014-02-27

申请人： Vanguard International Semiconductor Corporation

发明人： Tsung-Hsiung Lee ,  Shin-Cheng Lin

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/66659 ,  H01L21/265 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

摘要： A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

公开(公告)号：US09608057B2

公开(公告)日：2017-03-28

申请号：US15067279

申请日：2016-03-11

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shuhei Tatemichi ,  Takeyoshi Nishimura ,  Yasushi Niimura ,  Masanori Inoue

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L21/266

CPC分类号： H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7802

摘要： A MOS semiconductor device has a MOS structure, including a p− region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n− layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

公开(公告)号：US20170084743A1

公开(公告)日：2017-03-23

申请号：US15223937

申请日：2016-07-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li ,  Chun-Chen Yeh

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L21/324 ,  H01L21/762 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L21/823412 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

公开(公告)号：US20170077278A1

公开(公告)日：2017-03-16

申请号：US15263701

申请日：2016-09-13

申请人： Sensor Electronic Technology, Inc.

发明人： Grigory Simin ,  Michael Shur ,  Alexander Dobrinsky

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/7786 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/41758 ,  H01L29/42316

摘要： A semiconductor device including a device channel with a gate-drain region having a carrier concentration that varies laterally along a direction from the gate contact to the drain contact is provided. Lateral variation of the carrier concentration can be implemented by laterally varying one or more attributes of one or more layers located in the gate-drain region of the device.

摘要翻译： 提供一种半导体器件，其包括具有栅极 - 漏极区域的器件沟道，栅极 - 漏极区域具有沿着从栅极接触到漏极接触的方向横向变化的载流子浓度。 载流子浓度的横向变化可以通过横向改变位于器件的栅极 - 漏极区域中的一个或多个层的一个或多个属性来实现。

公开(公告)号：US09590053B2

公开(公告)日：2017-03-07

申请号：US14604885

申请日：2015-01-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsueh-Liang Chou ,  Dah-Chuen Ho ,  Hui-Ting Lu ,  Po-Chih Su ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/761 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L21/761 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7835

摘要： The present disclosure relates to a high voltage transistor device having a field plate, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to a drift region arranged between the gate electrode and the drain region. A field plate is located within a first inter-level dielectric layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts, having a same material as the field plate, vertically extend from a bottom surface of the first ILD layer to a top surface of the first ILD layer.

摘要翻译： 本公开涉及一种具有场板的高压晶体管器件及其形成方法。 在一些实施例中，高压晶体管器件具有设置在位于衬底内的源极区域和漏极区域之间的衬底上的栅电极。 电介质层从栅极电极上方横向延伸到布置在栅极电极和漏极区域之间的漂移区域。 场板位于覆盖衬底的第一级间介电层内。 场板从栅电极上方横向延伸到漂移区上方，并从电介质层垂直延伸到第一ILD层的顶表面。 具有与场板相同的材料的多个金属触点从第一ILD层的底表面垂直延伸到第一ILD层的顶表面。

公开(公告)号：US09570451B1

公开(公告)日：2017-02-14

申请号：US15151483

申请日：2016-05-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Tun-Jen Cheng

IPC分类号： H01L21/338 ,  H01L27/11 ,  H01L21/266 ,  H01L21/027 ,  H01L21/265

CPC分类号： H01L27/1116 ,  H01L21/0273 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/1104 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66492

摘要： A method of forming semiconductor devices. First, a substrate is provided, and a first implant area and a second implant area are defined in a mask pattern. Subsequently, a resist layer on the substrate is patterned using the mask pattern to form a first opening exposing the first implant area and a second opening to expose the second implant area. After that, an ion implantation process including a partial shadowing ion implant is processed, wherein the second implant area is implanted by the partial shadowing ion implant to a predetermined concentration, and the first implant area is substantially not implanted by the partial shadowing ion implant.

摘要翻译： 一种形成半导体器件的方法。 首先，提供基板，并且以掩模图案限定第一注入区域和第二注入区域。 随后，使用掩模图案对衬底上的抗蚀剂层进行构图，以形成暴露第一注入区域的第一开口和暴露第二注入区域的第二开口。 之后，处理包括部分阴离子离子注入的离子注入工艺，其中通过部分阴离子注入将第二注入区植入预定浓度，并且第一注入区基本上不被部分阴离子注入植入。

公开(公告)号：US20170040422A1

公开(公告)日：2017-02-09

申请号：US15227490

申请日：2016-08-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jae-Hyun JUNG ,  Chang-Ki JEON ,  Min-Hwan KIM ,  Kyu-Ok LEE ,  Jung-Kyung KIM ,  Jae-June JANG ,  Su-Yeon CHO

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/402 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device, including a substrate; a first conductive type well and a second conductive type body region at an upper portion of the substrate; a field plate on the first conductive type well, the field plate including a semiconductor material or an insulative nitride; and a gate electrode extending in a lateral direction on the substrate from a lateral portion of the second conductive type body region to a lateral portion of the first conductive type well, the gate electrode overlapping the field plate.

摘要翻译： 一种半导体器件，包括衬底; 在所述基板的上部的第一导电型阱和第二导电型体区; 在第一导电型阱上的场板，场板包括半导体材料或绝缘氮化物; 以及从所述第二导电型体区域的横向部分向所述第一导电型阱的侧面部分在所述基板上沿横向延伸的栅电极，所述栅电极与所述场板重叠。

公开(公告)号：US09559200B2

公开(公告)日：2017-01-31

申请号：US15052624

申请日：2016-02-24

申请人： Vanguard International Semiconductor Corporation

发明人： Shang-Hui Tu ,  Chih-Jen Huang ,  Jui-Chun Chang ,  Shin-Cheng Lin ,  Yu-Hao Ho ,  Wen-Hsin Lin

IPC分类号： H01L29/36 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L21/70 ,  H01L21/265 ,  H01L21/266 ,  H01L29/423

CPC分类号： H01L29/7801 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

摘要： A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

摘要翻译： 提供半导体器件。 该器件包括具有第一导电类型的衬底。 该器件还包括漏极区域，源极区域和设置在衬底中的阱区域。 阱区域设置在漏极区域和源极区域之间并且具有与第一导电类型相反的第二导电类型。 该器件还包括设置在阱区内的多个掺杂区域。 掺杂区域彼此垂直和水平地偏移。 每个掺杂区域包括具有第一导电类型的下部分和堆叠在下部区域上并具有第二导电类型的上部。

公开(公告)号：US09553081B2

公开(公告)日：2017-01-24

申请号：US14091626

申请日：2013-11-27

申请人： Enpirion, Inc.

发明人： Ashraf W. Lotfi ,  Jeffrey Demski ,  Anatoly Feygenson ,  Douglas Dean Lopata ,  Jay Norton ,  John D. Weld

IPC分类号： H01L27/06 ,  H01L23/482 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66 ,  H01L27/092 ,  H01L27/088 ,  H01L25/00 ,  H01L23/36 ,  H01L23/495 ,  H01L29/78 ,  H01L23/31 ,  H01L23/64 ,  H01L23/00 ,  H01L29/45 ,  H01L29/49 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L27/0207 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76895 ,  H01L21/8234 ,  H01L21/823871 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4824 ,  H01L23/495 ,  H01L23/49589 ,  H01L23/522 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48647 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

摘要翻译： 一种半导体器件及其形成方法，在一个实施例中包括形成有多个横向扩散的金属氧化物半导体（“LDMOS”）单元的半导体管芯。 半导体器件还包括电耦合到多个LDMOS电池的再分布层和分布在电分配层上并电耦合到再分配层的多个金属柱。

公开(公告)号：US09543149B2

公开(公告)日：2017-01-10

申请号：US14567398

申请日：2014-12-11

申请人： Texas Instruments Incorporated

发明人： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC分类号： H01L27/105 ,  H01L29/66 ,  H01L21/225 ,  H01L21/266 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

摘要翻译： 一种集成电路和方法，其具有具有埋入漂移区域的扩展漏极MOS晶体管，在埋入漂移区域和漏极接触之间的漏极扩散连接，以及在埋入漂移区域和沟道之间同时形成的通道端扩散连接，其中 沟道末端扩散链路是通过分段区域注入形成的，以将掺杂稀释到漏极端扩散链路中的掺杂量的不到三分之二。