公开(公告)号：US11814126B2

公开(公告)日：2023-11-14

申请号：US17275236

申请日：2019-10-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuichi Katsui ,  Takayuki Ikeda

IPC: B62J50/21 ,  G01S15/04 ,  G01S15/931 ,  G01S7/526 ,  H01L27/06 ,  H01L29/786

CPC classification number: B62J50/21 ,  G01S7/526 ,  G01S15/04 ,  G01S15/931 ,  H01L27/0688 ,  H01L29/7869

Abstract: To provide a driver alert system capable of improving the safety. A bicycle includes a first transmission circuit transmitting a first ultrasonic wave, a first receiving circuit receiving a second ultrasonic wave, an arithmetic circuit detecting the presence or absence of an object from the second ultrasonic wave, and a second transmission circuit transmitting a third ultrasonic wave. A driver wears a second housing including a second receiving circuit receiving the third ultrasonic wave. The arithmetic circuit includes a first selection circuit selecting a potential based on the second ultrasonic wave at a different timing, a plurality of signal retention circuits retaining a potential based on the second ultrasonic wave, a second selection circuit selecting any one of the plurality of signal retention circuits, and a signal processing circuit to which a signal selected in and output from the second selection circuit is input. The second selection circuit selects the plurality of signal retention circuits at different timings to generate a signal obtained by delaying the second ultrasonic wave. The third ultrasonic wave generated on the basis of the signal is transmitted to the second housing.

公开(公告)号：US20230343632A1

公开(公告)日：2023-10-26

申请号：US18215062

申请日：2023-06-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B10/125 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B12/053 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L2924/13062 ,  H01L23/3677

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

公开(公告)号：US11793005B2

公开(公告)日：2023-10-17

申请号：US18105041

申请日：2023-02-02

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L29/423 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/00 ,  H01L27/105 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/84 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7841 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105 ,  H01L2029/7857 ,  H01L2221/6835 ,  H10B12/056 ,  H10B12/36 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833

Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.

公开(公告)号：US11776954B2

公开(公告)日：2023-10-03

申请号：US17844573

申请日：2022-06-20

Applicant: Tokyo Electron Limited

Inventor： Mark I. Gardner ,  H. Jim Fulford

IPC: H01L27/06 ,  H01L21/8238

CPC classification number: H01L27/0688 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857

Abstract: Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.

公开(公告)号：US11776852B2

公开(公告)日：2023-10-03

申请号：US17347395

申请日：2021-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Ming Yu ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Fu-Hsiang Yang

IPC: H01L21/8234 ,  B82Y10/00 ,  H01L21/308 ,  H01L21/822 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  H01L21/3086 ,  H01L21/8221 ,  H01L21/823412 ,  H01L27/0688 ,  H01L27/0886 ,  H01L29/068 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78687 ,  H01L29/78696 ,  H01L21/823418 ,  H01L29/66469

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

公开(公告)号：US20230299060A1

公开(公告)日：2023-09-21

申请号：US18297928

申请日：2023-04-10

Applicant: Silicon Genesis Corporation

Inventor： Theodore E. FONG ,  Michael I. CURRENT

IPC: H01L25/10 ,  H01L21/822 ,  H01L25/00 ,  H01L21/762 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/8221 ,  H01L25/50 ,  H01L21/76254 ,  H01L24/83 ,  H01L24/94 ,  H01L27/0688

Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.

公开(公告)号：US11751409B2

公开(公告)日：2023-09-05

申请号：US17466442

申请日：2021-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC: H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC classification number: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

Abstract: To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-lth sub memory cell.

公开(公告)号：US20230275084A1

公开(公告)日：2023-08-31

申请号：US17738743

申请日：2022-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/822 ,  H01L23/50

CPC classification number: H01L27/0629 ,  H01L27/0688 ,  H01L21/823475 ,  H01L21/8221 ,  H01L23/50

Abstract: Provided is a semiconductor device that includes: at least one field-effect transistor and at least one PN junction device at a lateral side of the at least one field-effect transistor in a 1st layer; and at least one back side power delivery network (BSPDN) structure in a 2nd layer below the 1st layer, wherein the at least one BSPDN structure is configured to connect the at least one field-effect transistor to a voltage source.

公开(公告)号：US11744111B2

公开(公告)日：2023-08-29

申请号：US17839864

申请日：2022-06-14

Applicant: Japan Display Inc.

Inventor： Satoshi Maruyama

IPC: H01L27/00 ,  H10K59/121 ,  H01L27/12 ,  H10K59/131 ,  H01L27/06 ,  H10K59/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10K59/1213 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/1259 ,  H10K59/1216 ,  H10K59/131 ,  H01L27/0688 ,  H01L27/124 ,  H01L27/1222 ,  H01L27/1262 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78675 ,  H10K59/1201

Abstract: A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.

公开(公告)号：US11735585B2

公开(公告)日：2023-08-22

申请号：US17223829

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.