公开(公告)号：US11664229B2

公开(公告)日：2023-05-30

申请号：US17031131

申请日：2020-09-24

申请人： Applied Materials, Inc.

发明人： Yiyang Wan ,  Takashi Kuratomi

IPC分类号： C23C8/24 ,  C23C8/36 ,  C23C8/80 ,  H01L21/285 ,  H01J37/32

CPC分类号： H01L21/28518 ,  C23C8/24 ,  C23C8/36 ,  C23C8/80 ,  H01J37/3299 ,  H01J37/32449 ,  H01L21/28568 ,  H01J2237/3321

摘要： A method and apparatus for nitride capping of titanium materials via chemical vapor deposition techniques is provided. The method includes forming a titanium nitride layer upon a titanium material layer formed on a substrate. The titanium nitride layer is formed by exposing the titanium material layer to a hydrogen-rich nitrogen-containing plasma followed by exposing the titanium material layer to a nitrogen-rich nitrogen-containing plasma. The titanium nitride layer is then exposed to an argon plasma followed by exposing the titanium nitride layer to a halide soak process.

公开(公告)号：US20190214497A1

公开(公告)日：2019-07-11

申请号：US15892373

申请日：2018-02-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/7824 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66681

摘要： A semiconductor device includes: a first gate structure on a substrate; a first drain region having a first conductive type adjacent to one side of the first gate structure; a source region having the first conductive type adjacent to another side of the first gate structure; and a first body implant region having a second conductive type under part of the first gate structure.

公开(公告)号：US20190207010A1

公开(公告)日：2019-07-04

申请号：US15859492

申请日：2017-12-30

申请人： Texas Instruments Incorporated

发明人： Binghua Hu ,  Michael Allen Ball ,  Jarvis Benjamin Jacobs ,  James Robert Todd

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/02 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L27/092

CPC分类号： H01L29/665 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/32137 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/4175 ,  H01L29/456

摘要： An integrated circuit having silicide block integrated with CMOS transistors is formed by forming a silicide block layer of primarily silicon dioxide, free of silicon nitride and silicon oxy-nitride, at less than 400° C. prior to annealing the PMOS sources and drains. A spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The NMOS drain junctions are less than 120 nanometers; the NMOS halo regions include boron. The NMOS and PMOS transistors are laterally separated by an STI oxide layer. A wet deglaze process prior to metal silicide formation removes less than 25 percent of the silicide block layer, and exposes sides of the NMOS drains less than 20 percent of the drain junction depth. The metal silicide does not extend down the NMOS drains sides, directly adjacent to the STI oxide layer, more than 20 percent of the drain junction depth.

公开(公告)号：US20190189630A1

公开(公告)日：2019-06-20

申请号：US16186042

申请日：2018-11-09

申请人： Micron Technology, Inc.

发明人： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC分类号： H01L27/11556

CPC分类号： H01L27/11556 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

摘要： Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US20190148525A1

公开(公告)日：2019-05-16

申请号：US16230132

申请日：2018-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lien Huang ,  Tung Ying Lee

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/78 ,  H01L29/45 ,  H01L21/285 ,  H01L21/306

CPC分类号： H01L29/66795 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785

摘要： An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

公开(公告)号：US20190043992A1

公开(公告)日：2019-02-07

申请号：US15665888

申请日：2017-08-01

申请人： Globalfoundries Singapore Pte. Ltd.

发明人： Yuan Sun ,  Shyue Seng Tan

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L29/45 ,  H01L29/08 ,  H01L23/535 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/7881 ,  H01L21/28518 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/66825

摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a source, a drain, and a channel defined between the source and drain. A memory cell overlies the channel, where the memory cell includes a floating gate and a control gate overlying the floating gate. A block overlies a portion of the drain referred to as a blocked drain region, where the blocked drain region is adjacent to the channel. A drain silicide overlies the drain and terminates at the blocked drain region such that the blocked drain region is between the drain silicide and the channel.

公开(公告)号：US20180374758A1

公开(公告)日：2018-12-27

申请号：US16118953

申请日：2018-08-31

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. ANDERSON ,  Edward J. NOWAK

IPC分类号： H01L21/8234 ,  H01L29/786 ,  H01L21/285 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L21/764

CPC分类号： H01L21/823487 ,  H01L21/28518 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

公开(公告)号：US20180366550A1

公开(公告)日：2018-12-20

申请号：US16050939

申请日：2018-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L23/535 ,  H01L21/768

CPC分类号： H01L29/41791 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

公开(公告)号：US20180362568A1

公开(公告)日：2018-12-20

申请号：US16061049

申请日：2016-12-12

申请人： TOSOH CORPORATION ,  SAGAMI CHEMICAL RESEARCH INSTITUTE

发明人： Naoyuki KOISO ,  Yuki YAMAMOTO ,  Hiroyuki OIKE ,  Teppei HAYAKAWA ,  Taishi FURUKAWA ,  Ken-ichi TADA

IPC分类号： C07F17/02 ,  H01L29/49 ,  H01L29/45 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  C23C16/18

CPC分类号： C07F17/02 ,  C07F15/06 ,  C07F17/00 ,  C07F19/00 ,  C23C16/18 ,  H01L21/02175 ,  H01L21/02271 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76889 ,  H01L23/53238 ,  H01L29/456 ,  H01L29/4975

摘要： Provided is a cobalt complex which is useful for the production of a cobalt-containing thin film under conditions where no oxidizing gas is used. A cobalt complex represented by general formula (1) (wherein R1 represents a silyloxy group represented by general formula (2) (wherein R6, R7 and R8 independently represent an alkyl group having 1 to 6 carbon atoms); R2 represents a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, or a silyloxy group represented by general formula (2); R3, R4 and R5 independently represent a hydrogen atom or an alkyl group having 1 to 6 carbon atoms; and L represents a diene having 4 to 10 carbon atoms) is used.

公开(公告)号：US20180350936A1

公开(公告)日：2018-12-06

申请号：US16057324

申请日：2018-08-07

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/16 ,  H01L21/30 ,  H01L29/24 ,  H01L29/40 ,  H01L21/28

CPC分类号： H01L29/4941 ,  H01L21/02271 ,  H01L21/02592 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3003 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/16 ,  H01L29/24 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66575

摘要： A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.