公开(公告)号：US20230370170A1

公开(公告)日：2023-11-16

申请号：US18354379

申请日：2023-07-18

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

IPC: H04B10/80 ,  H04B10/516 ,  G11C5/04 ,  G11C5/06 ,  G11C11/42 ,  G02B6/42 ,  G11C5/14

CPC classification number: H04B10/80 ,  G02B6/4249 ,  G02B6/4274 ,  G11C5/04 ,  G11C5/06 ,  G11C5/141 ,  G11C11/42 ,  H04B10/516

Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.

公开(公告)号：US11810620B2

公开(公告)日：2023-11-07

申请号：US17458067

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki Takenaka ,  Akihiko Chiba ,  Teppei Higashitsuji ,  Kiyofumi Sakurai ,  Hiroaki Nakasa ,  Youichi Magome

IPC: G11C8/12 ,  G11C16/14 ,  G11C5/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/30 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

公开(公告)号：US20230352099A1

公开(公告)日：2023-11-02

申请号：US18184893

申请日：2023-03-16

Applicant: KIOXIA CORPORATION

Inventor： Koji KATO ,  Yuki SHIMIZU ,  Shuhei OKETA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  H01L23/528 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  H01L23/5283 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.

公开(公告)号：US20230343371A1

公开(公告)日：2023-10-26

申请号：US18347517

申请日：2023-07-05

Applicant: KIOXIA CORPORATION

Inventor： Masato SUGITA ,  Naoki KIMURA ,  Daisuke KIMURA

IPC: G11C5/04 ,  G06F16/9535 ,  G11C5/06 ,  G11C5/02 ,  G11C16/04 ,  G11C14/00 ,  G06F13/42

CPC classification number: G11C5/04 ,  G06F16/9535 ,  G11C5/06 ,  G11C5/02 ,  G11C16/04 ,  G11C5/063 ,  G11C14/0018 ,  G06F13/4282 ,  G06F2213/0032

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

公开(公告)号：US11792980B2

公开(公告)日：2023-10-17

申请号：US17532131

申请日：2021-11-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Ji Xia ,  Wei Xu ,  Pan Huang ,  Wenxiang Xu ,  Beihan Wang

IPC: H01L21/768 ,  H10B41/27 ,  G11C5/04 ,  G11C5/06 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/04 ,  G11C5/06 ,  G11C16/04 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H10B43/27

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a first source contact portion in a substrate, forming a dielectric stack over the first source contact portion, and forming a slit opening extending in the dielectric stack and exposing the first source contact portion. The method also includes forming a plurality of conductor layers through the slit opening and form a second source contact portion in the slit opening and in contact with the first source contact portion.

公开(公告)号：US11776632B2

公开(公告)日：2023-10-03

申请号：US17447594

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Reika Tanaka ,  Masumi Saitoh

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/10 ,  G11C5/06 ,  G11C16/30

CPC classification number: G11C16/14 ,  G11C5/06 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a semiconductor layer, a gate electrode, a gate insulating film disposed therebetween, first and second wirings connected to the semiconductor layer, and a third wiring connected to the gate electrode and is configured to execute a write operation, an erase operation, and a read operation. In the write operation, a write voltage of a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the erase operation, an erase voltage of a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the read operation, the write voltage or a voltage having a larger amplitude than that of the write voltage is supplied between the third wiring and at least one of the first wiring or the second wiring.

公开(公告)号：US11775460B2

公开(公告)日：2023-10-03

申请号：US17864023

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096 ,  G11C5/04

CPC classification number: G06F13/1689 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4096

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US20230307011A1

公开(公告)日：2023-09-28

申请号：US17901590

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Keita HASEGAWA ,  Keisuke NAKATSUKA

IPC: G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: G11C5/06 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first chip, a second chip, and a multiple of bonding pads. The first chip has a multiple of memory pillars that penetrate a multiple of wiring layers in a first direction. The second chip is bonded to the first chip. The multiple of bonding pads are provided at a bonding face between the first chip and the second chip. The multiple of bonding pads include a first bonding pad that electrically connects a first memory pillar among the multiple of memory pillars to one of a multiple of transistors, and a second bonding pad that neighbors the first bonding pad when seen from the first direction, and which electrically connects a second memory pillar among the multiple of memory pillars to one of the multiple of transistors. The second memory pillar does not neighbor the first memory pillar when seen from the first direction.

公开(公告)号：US11770934B2

公开(公告)日：2023-09-26

申请号：US17400087

申请日：2021-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Shih-Lien Linus Lu ,  Chia-En Huang ,  Yih Wang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H10B51/20 ,  G11C5/06 ,  H01L23/522

CPC classification number: H10B51/20 ,  G11C5/06 ,  G11C11/223 ,  H01L23/5221

Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

公开(公告)号：US11770928B2

公开(公告)日：2023-09-26

申请号：US17662800

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  James A. Cultra ,  Sri Sai Sivakumar Vegunta

IPC: G11C11/00 ,  H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/538 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5384 ,  H10B43/27

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.