公开(公告)号：US12144188B2

公开(公告)日：2024-11-12

申请号：US18099777

申请日：2023-01-20

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Hongqi Li

IPC: H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.

公开(公告)号：US20220037400A1

公开(公告)日：2022-02-03

申请号：US16983843

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  James A. Cultra

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/092 ,  H01L45/00 ,  H01L23/538

Abstract: Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

公开(公告)号：US20210183697A1

公开(公告)日：2021-06-17

申请号：US17188734

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/48

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

公开(公告)号：US20200235007A1

公开(公告)日：2020-07-23

申请号：US16773716

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/288

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

公开(公告)号：US10286517B2

公开(公告)日：2019-05-14

申请号：US15671895

申请日：2017-08-08

Applicant: Micron Technology, Inc.

Inventor： Jian Zhou ,  Hongqi Li ,  James A. Cultra

IPC: B24B37/013 ,  G01N21/31 ,  H01L21/66 ,  H01L21/306

Abstract: Some embodiments include an apparatus having a polishing mechanism configured to polish a surface of a wafer. The polishing mechanism converts fresh slurry to used slurry during a polishing process. At least one emitter is configured to direct electromagnetic radiation onto or through the used slurry. At least one detector is configured to detect transmittance of the electromagnetic radiation through the used slurry or reflection of the electromagnetic radiation from the used slurry. An identification system is coupled with the at least one detector and is configured to identify a property of the used slurry indicating that an endpoint of the polishing process has been reached. Control circuitry is coupled with the identification system and is configured to stop the polishing process based on receiving a trigger from the identification system. Some embodiments include polishing methods.

公开(公告)号：US09911643B2

公开(公告)日：2018-03-06

申请号：US15182462

申请日：2016-06-14

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Gowrisankar Damarla ,  Robert J. Hanson ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

公开(公告)号：US09754825B2

公开(公告)日：2017-09-05

申请号：US14815560

申请日：2015-07-31

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L21/288

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

公开(公告)号：US09305865B2

公开(公告)日：2016-04-05

申请号：US14068837

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Jian He ,  Lalapet Rangan Vasudevan ,  Kyle K. Kirby ,  Hongqi Li

IPC: H01L21/00 ,  H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Abstract translation: 制造具有贯通衬底通孔（TSV）的半导体器件和半导体器件的方法。 制造半导体器件的方法的一个实施例包括通过电介质结构和半导体衬底的至少一部分形成开口，以及形成具有衬在开口上的第一部分的电介质衬垫材料和在外表面上的第二部分 电介质结构横向于开口外侧。 该方法还包括去除导电材料，使得电介质衬垫材料的第二部分被暴露，并且在电耦合到TSV的电介质衬垫材料的第二部分中形成镶嵌导电线。

公开(公告)号：US20150115445A1

公开(公告)日：2015-04-30

申请号：US14068837

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Jian He ,  Lalapet Rangan Vasudevan ,  Kyle K. Kirby ,  Hongqi Li

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Abstract translation: 制造具有贯通衬底通孔（TSV）的半导体器件和半导体器件的方法。 制造半导体器件的方法的一个实施例包括通过电介质结构和半导体衬底的至少一部分形成开口，以及形成具有衬在开口上的第一部分的电介质衬垫材料和在外表面上的第二部分 电介质结构横向于开口外侧。 该方法还包括去除导电材料，使得电介质衬垫材料的第二部分被暴露，并且在电耦合到TSV的电介质衬垫材料的第二部分中形成镶嵌导电线。

公开(公告)号：US12237217B2

公开(公告)日：2025-02-25

申请号：US17188734

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/538

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.