公开(公告)号：US20170352412A1

公开(公告)日：2017-12-07

申请号：US15175201

申请日：2016-06-07

Applicant: Nantero, Inc.

Inventor： Qawi Harvard

IPC: G11C13/00 ,  H01L51/05

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C13/025 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/82 ,  H01L51/0558

Abstract: Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements by sensing current flow. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements without the need for in situ selection devices or other current controlling devices. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can reduce the impact of sneak current when determining resistive states of resistive change elements.

公开(公告)号：US09837154B2

公开(公告)日：2017-12-05

申请号：US15500472

申请日：2015-04-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/77

Abstract: One example includes a resistive random access memory (RRAM) system. The system includes a resistive memory element to store a binary state based on a resistance of the resistive memory element. The system also includes an RRAM write circuit to generate a current through the resistive memory element to provide a write voltage across the resistive memory element to set the resistance of the resistive memory element. The system further includes a write shutoff circuit to monitor a change in the write voltage as a function of time to deactivate the RRAM write circuit in response to a change in the binary state of the resistive memory element.

公开(公告)号：US20170330622A1

公开(公告)日：2017-11-16

申请号：US15592999

申请日：2017-05-11

Applicant: Crossbar, Inc.

Inventor： Lin Shih Liu ,  Hagop Nazarian

IPC: G11C14/00 ,  G11C13/00 ,  G11C11/419

CPC classification number: G11C14/009 ,  G11C11/412 ,  G11C11/419 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  H03K19/1776

Abstract: Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

公开(公告)号：US20170316825A1

公开(公告)日：2017-11-02

申请号：US15487303

申请日：2017-04-13

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Bastien Giraud ,  Alexandre Levisse ,  Jean-Philippe Noel

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.

公开(公告)号：US09806256B1

公开(公告)日：2017-10-31

申请号：US15299919

申请日：2016-10-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ming-Che Wu ,  Chuanbin Pan ,  Guangle Zhou ,  Tanmay Kumar

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/124 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/51 ,  G11C2213/52 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1675

Abstract: A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.

公开(公告)号：US20170309336A1

公开(公告)日：2017-10-26

申请号：US15646933

申请日：2017-07-11

Applicant: Renesas Electronics Corporation

Inventor： Takashi HASE ,  Naoya FURUTAKE ,  Koji MASUZAKI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79 ,  G11C2213/82

Abstract: A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells. The control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state.

公开(公告)号：US09783255B2

公开(公告)日：2017-10-10

申请号：US15197185

申请日：2016-06-29

Applicant: Nantero Inc.

Inventor： Claude L. Bertin ,  C. Rinn Cleavelin ,  Thomas Rueckes ,  X. M. Henry Huang ,  H. Montgomery Manning

IPC: H01L29/02 ,  B62J7/06

CPC classification number: B62J7/06 ,  B82Y10/00 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/249 ,  H01L27/285 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/861 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675 ,  H01L51/0048 ,  H01L51/0579

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

公开(公告)号：US09780115B2

公开(公告)日：2017-10-03

申请号：US15188273

申请日：2016-06-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/24 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11548 ,  H01L27/11575 ,  G11C13/00 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L45/00

CPC classification number: H01L27/11582 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C2213/71 ,  H01L21/28273 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/06

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US09779813B2

公开(公告)日：2017-10-03

申请号：US15222861

申请日：2016-07-28

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsiang-Lan Lung ,  Hsin-Yi Ho ,  Scott C. Lewis ,  Richard C. Jordan

IPC: G11C8/16 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C7/1039 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

Abstract: A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.

公开(公告)号：US09767901B1

公开(公告)日：2017-09-19

申请号：US15245607

申请日：2016-08-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  Gary Gibson ,  Naveen Muralimanohar ,  Martin Foltin ,  Greg Astfalk

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

Abstract: An integrated circuit is provided. In an example, the integrated circuit includes a first address line, a selector device electrically coupled to the first address lines, and a memory device electrically coupled between the selector device and a second address line. The selector device has a first I-V response in a first current direction and a second I-V response in a second current direction that is different from the first I-V response.