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公开(公告)号：US10734074B2
公开(公告)日：2020-08-04
申请号：US16054958
申请日：2018-08-03
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.
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公开(公告)号：US20190237137A1
公开(公告)日：2019-08-01
申请号：US16063804
申请日：2016-01-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Xheng , John Paul Strachan
CPC classification number: G11C13/0026 , G06F17/16 , G06G7/16 , G11C11/1659 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C2013/0057 , G11C2213/32 , G11C2213/77
Abstract: In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements.
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公开(公告)号：US10216720B2
公开(公告)日：2019-02-26
申请号：US15336907
申请日：2016-10-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G06F17/27
Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.
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公开(公告)号：US10089574B2
公开(公告)日：2018-10-02
申请号：US15264768
申请日：2016-09-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Sity Lam , Le Zheng
Abstract: Examples disclosed herein relate to neuron circuits and methods for generating neuron circuit outputs. In some of the disclosed examples, a neuron circuit includes a memristor and first and second current mirrors. The first current mirror may source a first current through the memristor and the second current mirror may sink a second current through the memristor. The memristor may generate a voltage output as a function of the sourced first current and the sunk second current through the memristor.
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公开(公告)号：US09972387B2
公开(公告)日：2018-05-15
申请号：US15325040
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Martin Foltin , Yoocharn Jeon , Brent Buchanan , Erik Ordentlich , Naveen Muralimanohar , James S. Ignowski , Jacquelyn M. Ingemi
CPC classification number: G11C13/004 , G11C7/06 , G11C13/0038 , G11C13/0059 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2207/068
Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.
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公开(公告)号：US09972385B2
公开(公告)日：2018-05-15
申请号：US15328269
申请日：2014-11-04
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Phillip David Misek , Brent Buchanan
IPC: G11C13/00
CPC classification number: G11C13/0023 , G11C13/0021 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C16/06 , G11C16/10 , G11C2013/0073 , G11C2213/77 , G11C2213/79
Abstract: Example implementations relate to memory array drivers. For example, a memory array includes a memory cell. The memory array also includes a bit line coupled to the memory cell and a word line coupled to the memory cell. The memory array further includes a first memory array driver having a first terminal and a second terminal. The first terminal is coupled to the bit line. The second terminal is coupled to the word line. The memory array further includes a second memory array driver having a third terminal and a fourth terminal. The third terminal is coupled to the bit line. The fourth terminal is coupled to the word line.
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公开(公告)号：US20180114569A1
公开(公告)日：2018-04-26
申请号：US15570951
申请日：2016-03-11
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Brent Buchanan , Le Zheng
CPC classification number: G11C11/54 , G06F9/06 , G06N3/0454 , G06N3/0635 , G11C7/1006 , G11C7/1012 , G11C13/0007 , G11C13/0069
Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.
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公开(公告)号：US20180114556A1
公开(公告)日：2018-04-26
申请号：US15568458
申请日：2015-06-05
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan
CPC classification number: G11C7/24 , G11C5/06 , G11C13/0007 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C29/50 , G11C2013/0045 , G11C2013/0054 , G11C2013/0078 , G11C2029/5002 , H02H1/0061 , H02H9/046
Abstract: In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor.
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公开(公告)号：US20180095722A1
公开(公告)日：2018-04-05
申请号：US15282021
申请日：2016-09-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
CPC classification number: G06F7/523 , G06F7/5443 , G06F2207/4802 , G06F2207/4828 , G11C13/0007 , G11C13/0028 , G11C13/004
Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
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公开(公告)号：US20180025790A1
公开(公告)日：2018-01-25
申请号：US15216589
申请日：2016-07-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Emmanuelle J. Merced Grafals , Brent Buchanan , Le Zheng
CPC classification number: G11C29/789 , G11C13/0021 , H01L45/04 , H01L45/16
Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.
