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公开(公告)号：US20160365144A1
公开(公告)日：2016-12-15
申请号：US15099660
申请日：2016-04-15
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/004 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0092 , G11C2213/79 , G11C2213/82
摘要： Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.
摘要翻译： 包括各自包括电阻变化元件和控制电路的存储单元。 该电路执行On写入处理，以将存储单元中的On写入脉冲施加在电阻变化元件的电阻值低于第一基准值的电阻状态，以及用于 对具有第二参考值或更高的高电阻状态的ON写入脉冲施加具有相反极性的OFF写入脉冲。 该电路在On写入处理中应用与On写入脉冲具有相同极性的试用脉冲，其脉冲宽度短于On写入脉冲的脉冲宽度，并且具有与On 写入脉冲，按此顺序将“写入”脉冲应用于单元格。
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公开(公告)号：US20160276026A1
公开(公告)日：2016-09-22
申请号：US14962777
申请日：2015-12-08
发明人： Takashi HASE , Naoya FURUTAKE , Koji MASUZAKI
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/72 , G11C2213/79 , G11C2213/82
摘要： When writing ReRAM cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an Off writing process of applying Off writing pulse to a memory cell to turn it into high resistance state and an On writing process of applying On writing pulse to turn it into low resistance state. The control circuitry, when the memory cell is placed in low resistance state, after applying Off writing pulse, applies a reading pulse for a verify process of reading whether it is placed in high or low resistance state. If the memory cell is not placed in high resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising On writing pulse, applies Off writing pulse with extended pulse width and executes the verify process in mentioned order.
摘要翻译： 当写入ReRAM单元时，追求将单元设置在足够高或低电阻状态，同时防止过度写入。 公开了一种包括存储单元的半导体存储装置，每个存储单元包括可变电阻元件，以及控制电路，其执行将写入脉冲施加到存储器单元以将其变为高电阻状态的关闭写入处理以及应用于On 写入脉冲将其变为低电阻状态。 当存储单元置于低电阻状态时，控制电路在施加关闭写入脉冲之后，施加读取脉冲以进行读取的验证处理是否处于高电平或低电阻状态。 如果作为验证处理的结果，存储单元未被置于高电阻状态，则控制电路施加包括在写入脉冲中的复位脉冲，施加具有扩展脉冲宽度的关闭写入脉冲，并按照上述顺序执行验证处理。
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公开(公告)号：US20170309336A1
公开(公告)日：2017-10-26
申请号：US15646933
申请日：2017-07-11
发明人： Takashi HASE , Naoya FURUTAKE , Koji MASUZAKI
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/72 , G11C2213/79 , G11C2213/82
摘要： A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells. The control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state.
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公开(公告)号：US20170133434A1
公开(公告)日：2017-05-11
申请号：US15334846
申请日：2016-10-26
发明人： Makoto UEKI , Koji MASUZAKI , Takashi HASE , Yoshihiro HAYASHI
CPC分类号： H01L27/2481 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1625 , H01L45/1633
摘要： A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.
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