公开(公告)号：US11984478B2

公开(公告)日：2024-05-14

申请号：US17341745

申请日：2021-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu Wen Wang ,  Chih-Teng Liao ,  Chih-Shan Chen ,  Jui Fu Hsieh ,  Dave Lo

IPC: H01L21/8238 ,  H01L25/065 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H10B10/00 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L25/0655 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H10B10/12 ,  H01L29/41791

Abstract: A method includes forming a first portion of a spacer layer over a first fin and a second portion of the spacer layer over a second fin, performing a first etching process to recess the first portion of the spacer layer with respect to the second portion of the spacer layer to form first spacers on sidewalls of the first fin, subsequently performing a second etching process to recess the second portion of the spacer layer with respect to the first spacers to form second spacers on sidewalls of the second fin, where the second spacers are formed to a height greater than that of the first spacers, and forming a first epitaxial source/drain feature and a second epitaxial source/drain feature between the first spacers and the second spacers, respectively, where the first epitaxial source/drain feature is larger than that of the second epitaxial source/drain feature.

公开(公告)号：US20240153550A1

公开(公告)日：2024-05-09

申请号：US18412380

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Atuk KATOCH

IPC: G11C11/417 ,  G11C5/14 ,  H10B10/00

CPC classification number: G11C11/417 ,  G11C5/148 ,  H10B10/12

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

公开(公告)号：US11978634B2

公开(公告)日：2024-05-07

申请号：US17664930

申请日：2022-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Jie Liu ,  Chun-Feng Nieh ,  Huicheng Chang

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851 ,  H10B10/12

Abstract: A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.

公开(公告)号：US20240138135A1

公开(公告)日：2024-04-25

申请号：US18405160

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy LIAW

IPC: H10B10/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H10B10/12 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  G11C11/412

Abstract: A memory device including a rectangular shaped via for at least one Vss node connection. In some embodiments, the rectangular shaped via has a length/width of greater than 1.5. The rectangular shaped via may be disposed on the Via0 and/or Via1 layer interfacing a first metal layer (e.g., M1). The memory cell may also include circular/square shaped vias having a length/width of between approximately 0.8 and 1.2. The circular/square shaped vias may be coplanar with the rectangular shaped vias.

公开(公告)号：US11968817B2

公开(公告)日：2024-04-23

申请号：US17682061

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417

CPC classification number: H10B10/12 ,  H01L21/02063 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41791

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US11961767B2

公开(公告)日：2024-04-16

申请号：US17967511

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Jeffrey S. Leib ,  Srijit Mukherjee ,  Vinay Bhagwat ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/8238 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00

CPC classification number: H01L21/823814 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7854 ,  H10B10/12

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

公开(公告)号：US11948829B2

公开(公告)日：2024-04-02

申请号：US17682425

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang

IPC: H01L21/762 ,  H01L21/3065 ,  H10B10/00

CPC classification number: H01L21/76224 ,  H01L21/3065 ,  H01L21/76232 ,  H10B10/12

Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

公开(公告)号：US20240105257A1

公开(公告)日：2024-03-28

申请号：US18165678

申请日：2023-02-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jhon Jhy LIAW

IPC: G11C11/412 ,  G11C11/417 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/417 ,  H10B10/12

Abstract: A semiconductor device includes first and second active areas, first and second gate structures, and first to third conductive segments. The first and second active areas extend along the first direction. The first and second gate structures cross over the first and second active areas. The first conductive segment crosses over the first and second gate structures, stores a first data signal, and is coupled to the first gate structure, the first and second active areas. The second conductive segment crosses over the first and second gate structures, stores a first complementary data signal, and is coupled to the second gate structure, the first and second active areas. The third conductive segment crosses over the first and second gate structures, and is coupled to the second active area. The first to third conductive segments are arranged in order along a second direction different from the first direction.

公开(公告)号：US11935882B2

公开(公告)日：2024-03-19

申请号：US17403788

申请日：2021-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jhon Jhy Liaw

IPC: H01L27/02 ,  G11C11/412 ,  H01L23/522 ,  H01L23/528 ,  H10B10/00

CPC classification number: H01L27/0207 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device including a static random access memory (SRAM) device includes a first SRAM array including a first plurality of bit cells arranged in a matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts.

公开(公告)号：US20240090190A1

公开(公告)日：2024-03-14

申请号：US18519559

申请日：2023-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Jen CHEN ,  Wen-Hsi LEE ,  Ling-Sung WANG ,  I-Shan HUANG ,  Chan-yu HUNG

IPC: H10B10/00 ,  G06F30/39 ,  H01L23/528 ,  H01L27/088

CPC classification number: H10B10/12 ,  G06F30/39 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/785

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.