公开(公告)号：US20170203108A1

公开(公告)日：2017-07-20

申请号：US15477621

申请日：2017-04-03

申请人： Advanced Bionics AG

发明人： Kurt J. Koester ,  Chuladatta Thenuwara ,  Timothy Beerling ,  Mark B. Downing ,  David Stuursma ,  Logan P. Palmer

IPC分类号： A61N1/375 ,  A61N1/36 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  A61N1/05 ,  H01L23/055

CPC分类号： A61N1/3754 ,  A61N1/0541 ,  A61N1/36036 ,  H01L21/486 ,  H01L23/045 ,  H01L23/055 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/165 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/00

摘要： A device includes a hermetically sealed case with electronic circuitry housed within. One surface of the hermetically sealed case includes a metallic plate and a co-fired ceramic electrical feedthrough with a number of vias. The co-fired ceramic electrical feedthrough is hermetically joined to the metallic plate and a hybrid circuit is connected to the feedthrough.

公开(公告)号：US09704788B2

公开(公告)日：2017-07-11

申请号：US14665735

申请日：2015-03-23

申请人： General Electric Company

发明人： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC分类号： H01L23/48 ,  H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

摘要： A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

公开(公告)号：US09698088B2

公开(公告)日：2017-07-04

申请号：US15135364

申请日：2016-04-21

申请人： Samsung Electronics Co., Ltd.

发明人： Heungkyu Kwon ,  Kang Joon Lee ,  JaeWook Yoo ,  Su-Chang Lee

IPC分类号： H01L23/498 ,  H01L23/488 ,  H01L23/16 ,  H01L23/18 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

CPC分类号： H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

摘要： Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

公开(公告)号：US09691736B2

公开(公告)日：2017-06-27

申请号：US14881558

申请日：2015-10-13

申请人： SFI Electronics Technology Inc.

发明人： Ching-Hohn Lien ,  Xing-Xiang Huang ,  Hsing-Tsai Huang ,  Hong-Zong Xu ,  Yi-Wei Chen

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/02 ,  H01L23/15 ,  H01L23/31 ,  H01L29/861 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40 ,  H01L25/065

CPC分类号： H01L24/97 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/7813 ,  H01L23/02 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0652 ,  H01L29/861 ,  H01L2224/06181 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32168 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/186 ,  H05K1/117 ,  H05K1/144 ,  H05K1/145 ,  H05K3/403 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83

摘要： A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

公开(公告)号：US09691735B2

公开(公告)日：2017-06-27

申请号：US14585857

申请日：2014-12-30

申请人： SFI Electronics Technology Inc.

发明人： Ching-Hohn Lien ,  Xing-Xiang Huang ,  Hsing-Tsai Huang ,  Hong-Zong Xu ,  Yi-Wei Chen

IPC分类号： H01L27/15 ,  H01L29/267 ,  H01L31/12 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/02 ,  H01L23/15 ,  H01L23/31 ,  H01L29/861 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40 ,  H01L25/065

CPC分类号： H01L24/97 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/7813 ,  H01L23/02 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0652 ,  H01L29/861 ,  H01L2224/06181 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32168 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/186 ,  H05K1/117 ,  H05K1/144 ,  H05K1/145 ,  H05K3/403 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83

摘要： A miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from a process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

公开(公告)号：US20170176260A1

公开(公告)日：2017-06-22

申请号：US14975938

申请日：2015-12-21

申请人： INTEL CORPORATION

发明人： Shelby Ferguson ,  Rashelle Yee ,  Russell S. Aoki ,  Michael Hui ,  Jonathon Robert Carstens ,  Joseph J. Jasniewski

IPC分类号： G01K7/16 ,  H01L23/34

CPC分类号： G01K7/16 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/345 ,  H01L23/473 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2224/45099

摘要： Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.

公开(公告)号：US09666776B2

公开(公告)日：2017-05-30

申请号：US14513278

申请日：2014-10-14

申请人： SHARP KABUSHIKI KAISHA

发明人： Toshiyuki Takada

IPC分类号： H01L33/62 ,  H01L33/48 ,  H01L33/54 ,  H01L33/64 ,  H01L23/00 ,  H01L33/52 ,  H01L33/60

CPC分类号： H01L33/62 ,  H01L24/97 ,  H01L33/486 ,  H01L33/52 ,  H01L33/54 ,  H01L33/60 ,  H01L33/641 ,  H01L33/647 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/85

摘要： A semiconductor light emitting device that is excellent in radiating heat and that can be molded into a sealing shape having intended optical characteristics by die molding is provided. The semiconductor light emitting device includes: a lead frame including a plate-like semiconductor light emitting element mounting portion having an LED chip mounted on a main surface, and a plate-like metal wire connecting portion extending over a same plane as the semiconductor light emitting element mounting portion; a metal wire electrically connecting the LED chip and the metal wire connecting portion; a thermosetting resin molded by die molding or dam-sheet molding so as to completely cover the LED chip and the metal wire; and a resin portion provided to surround the lead frame and having the thickness not greater than the thickness of the lead frame.

公开(公告)号：US09653661B2

公开(公告)日：2017-05-16

申请号：US12926253

申请日：2010-11-04

申请人： Yoshinobu Suehiro ,  Seiji Yamaguchi ,  Katsunori Arakane ,  Koji Tasumi

发明人： Yoshinobu Suehiro ,  Seiji Yamaguchi ,  Katsunori Arakane ,  Koji Tasumi

IPC分类号： H01L21/603 ,  H01L33/56 ,  H01L33/54 ,  H01L23/00 ,  H01L25/075 ,  H01L33/48

CPC分类号： H01L33/56 ,  H01L24/97 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/54 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2933/005 ,  H01L2924/00

摘要： A method of manufacturing a light-emitting device includes a hole forming process for forming a through-hole that continues from a front surface to a back surface of a mounting substrate, a pattern forming process for continuously forming a circuit pattern on an inner surface of the through-hole in the mounting substrate, from an end portion of the through-hole on the front surface of the mounting substrate to a mounting portion of a light-emitting element, and on a periphery of the through-hole on the back surface of the mounting substrate, a mounting process for mounting the light-emitting element on the mounting portion, and a hot pressing process in that an inorganic material softened by heating is placed on the surface of the mounting substrate and is advanced into the through-hole while sealing the light-emitting element by pressing and bonding the inorganic material to the surface of the mounting substrate.

公开(公告)号：US20170133311A1

公开(公告)日：2017-05-11

申请号：US15410688

申请日：2017-01-19

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chin-Li KAO ,  Chang-Chi LEE ,  Yi-Shao LAI

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/15738 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15798 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2224/0401

摘要： The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

公开(公告)号：US09640518B2

公开(公告)日：2017-05-02

申请号：US15067203

申请日：2016-03-11

申请人： BRIDGE SEMICONDUCTOR CORPORATION

发明人： Charles W. C. Lin ,  Chia-Chung Wang

IPC分类号： H01L23/34 ,  H01L25/10 ,  H01L23/36 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L25/105 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/15793 ,  H01L2924/16153 ,  H01L2924/16172 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by forming through openings that extend through a metallic carrier between first and second surfaces of the metallic carrier, attaching a chip-on-interposer subassembly on the metallic carrier using an adhesive, with the chip inserted into a cavity of the metallic carrier, and with the chip-on-interposer subassembly attached to the metallic carrier, forming first and second buildup circuitry on a first surface of the interposer and the second surface of the metallic carrier, respectively, and subsequently forming plated through holes that extend into the through openings to provide electrical and thermal connections between the first and second buildup circuitry. The method and resulting device advantageously provides vertical signal routing and stacking capability for a semiconductor package.