公开(公告)号：US20230253355A1

公开(公告)日：2023-08-10

申请号：US18300493

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/13 ,  H01L24/14 ,  H01L24/11 ,  H01L25/50 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/2064 ,  H01L2924/384 ,  H01L2224/13012 ,  H01L2224/05552 ,  H01L2224/81345 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2924/01322 ,  Y10T428/24479 ,  Y10T428/12493 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2224/81191 ,  H01L2224/16238 ,  H01L2224/13147 ,  H01L2224/131 ,  H01L2224/13083 ,  H01L2224/13082 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/14051 ,  H01L2224/10145 ,  H01L2224/1412

Abstract: The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.

公开(公告)号：US20180040659A1

公开(公告)日：2018-02-08

申请号：US15783616

申请日：2017-10-13

Applicant: OLYMPUS CORPORATION

Inventor： Takashi NAKAYAMA

IPC: H01L27/146 ,  H01L23/00 ,  H04N5/225

CPC classification number: H01L27/14636 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L27/14 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/14153 ,  H01L2224/16227 ,  H01L2224/17517 ,  H04N5/2253 ,  H04N5/2257

Abstract: An image pickup apparatus includes: an image pickup device including a light receiving surface, an opposite surface, and an inclined surface, and provided with light receiving surface electrodes formed on the light receiving surface; cover glass joined so as to cover the light receiving surface; and a wiring board including second bond electrodes, wherein back surfaces of the light receiving surface electrodes being exposed to an opposite surface side, extended wiring patterns extended from the respective back surfaces of the light receiving surface electrodes through the inclined surface to the opposite surface, each of the extended wiring patterns including a first bond electrode, and the first bond electrode and the second bond electrode being bonded through a bump.

公开(公告)号：US09875674B2

公开(公告)日：2018-01-23

申请号：US14474563

申请日：2014-09-02

Applicant: Japan Display Inc.

Inventor： Chunhan Zhang ,  Yoshihiro Kotani

IPC: H01L23/498 ,  G09G3/00 ,  H01L27/12 ,  G02F1/1345 ,  H01L21/66 ,  H01L23/00

CPC classification number: G09G3/006 ,  G02F1/13454 ,  G02F1/13458 ,  G02F2203/69 ,  H01L22/34 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13013 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/16227 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9212 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/07811

Abstract: A display device includes, on a TFT substrate, a driver IC having a first bump and a second bump, a first terminal and a second terminal connecting respectively to the first bump and the second bump, and wiring interconnecting the first terminal and the second terminal. The driver IC also includes a resistance detection circuit that detects resistance between the first bump and the second bump.

公开(公告)号：US09824992B2

公开(公告)日：2017-11-21

申请号：US15353197

申请日：2016-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure may have a first conductive structure and a second conductive structure arranged over a first substrate. A bump structure is arranged between the first conductive structure and a second substrate. A solder layer is configured to electrically couple the first conductive structure and the bump structure. The bump structure has a recess that is configured to reduce a protrusion of the solder layer in a direction extending from the first conductive structure to the second conductive structure.

公开(公告)号：US20170062371A1

公开(公告)日：2017-03-02

申请号：US15353197

申请日：2016-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure may have a first conductive structure and a second conductive structure arranged over a first substrate. A bump structure is arranged between the first conductive structure and a second substrate. A solder layer is configured to electrically couple the first conductive structure and the bump structure. The bump structure has a recess that is configured to reduce a protrusion of the solder layer in a direction extending from the first conductive structure to the second conductive structure.

Abstract translation: 在一些实施例中，本公开涉及半导体结构。 半导体结构可以具有布置在第一衬底上的第一导电结构和第二导电结构。 凸起结构布置在第一导电结构和第二基板之间。 焊料层被配置为电耦合第一导电结构和凸块结构。 凸起结构具有凹部，其被构造成在从第一导电结构延伸到第二导电结构的方向上减小焊料层的突起。

公开(公告)号：US20170053884A1

公开(公告)日：2017-02-23

申请号：US15182581

申请日：2016-06-14

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14134 ,  H01L2224/14153 ,  H01L2224/14177 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/19102 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A ball grid array for an integrated circuit package includes an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package. According to one embodiment, the connection points are solder balls mounted on a lower surface of the integrated circuit package.

Abstract translation: 用于集成电路封装的球栅阵列包括源自在集成电路封装的至少一个或多个部分中重复的六边形图案的基本单元的连接点阵列。 根据一个实施例，连接点是安装在集成电路封装的下表面上的焊球。

公开(公告)号：US20170005055A1

公开(公告)日：2017-01-05

申请号：US15264588

申请日：2016-09-13

Applicant: Renesas Electronics Corporation

Inventor： Shinya Suzuki

IPC: H01L23/00 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1345 ,  H01L23/528 ,  G02F1/133

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract translation: 一种提高半导体芯片的凸块电极与安装基板的配线之间的耦合可靠性的技术，更具体地说，即使在布线位于突起电极下方的顶部布线层中时也能保证凸块电极的平坦度的技术，由此 提高凸起电极和形成在玻璃基板上的布线之间的耦合的可靠性。 在突起电极的非重叠区域下方的顶部布线层中形成由电力线或信号线构成的布线和虚设图案。 虚拟图案位于填充布线之间的空间以减少由布线引起的不规则和顶部布线层中的空间。 形成为覆盖顶部布线层的表面保护膜被CMP平坦化。

公开(公告)号：US20160126264A1

公开(公告)日：2016-05-05

申请号：US14994016

申请日：2016-01-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinya SUZUKI

IPC: H01L27/13 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L24/14 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/13 ,  H01L29/7833 ,  H01L2224/02122 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05075 ,  H01L2224/051 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/14153 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/93 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

公开(公告)号：US09129816B2

公开(公告)日：2015-09-08

申请号：US13422846

申请日：2012-03-16

Applicant: Jie Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Ying-Ju Chen

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Ying-Ju Chen

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/482

CPC classification number: H01L22/34 ,  H01L22/30 ,  H01L22/32 ,  H01L23/4824 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/06505 ,  H01L2224/11015 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/014

Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Abstract translation: 提供了一种用于测试电气连接的系统和方法。 在一个实施例中，可以制造一个或多个浮动焊盘，以与下部焊接金属化结构电连接。 然后可以进行测试以通过浮动垫测量底部金属化结构的电特性，以测试缺陷。 或者，可以在下凸点金属化上形成导电连接，并且可以在导电连接和下凸点金属化一起进行测试。

公开(公告)号：US20140004661A1

公开(公告)日：2014-01-02

申请号：US14013304

申请日：2013-08-29

Applicant: Renesas Electronics Corporation

Inventor： Jumpei KONNO ,  Takafumi NISHITA ,  Nobuhiro KINOSHITA ,  Kazunori HASEGAWA ,  Michiaki SUGIYAMA

IPC: H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Abstract translation: 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。