公开(公告)号：US09558966B2

公开(公告)日：2017-01-31

申请号：US14755700

申请日：2015-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Wei-Cheng Wu ,  Chien-Fu Tseng

IPC: H01L23/28 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/12 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material around the integrated circuit die mounting region. An interconnect structure is over the molding material and the integrated circuit die mounting region. A protection pattern is in a perimeter region of the package around the interconnect structure. The protection pattern includes a first conductive feature that is vertical within the package near a second conductive feature. The first conductive feature has a first width, and the second conductive feature has a second width. The second width is greater than the first width.

Abstract translation: 公开了半导体器件封装，封装方法和封装半导体器件。 在一些实施例中，用于半导体器件的封装包括集成电路管芯安装区域和围绕集成电路管芯安装区域的成型材料。 互连结构在成型材料和集成电路管芯安装区域之上。 保护图案位于互连结构周围的封装的周边区域中。 保护图案包括在第二导电特征附近的封装内的垂直的第一导电特征。 第一导电特征具有第一宽度，并且第二导电特征具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US09372206B2

公开(公告)日：2016-06-21

申请号：US14833950

申请日：2015-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/00 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  G01R31/26 ,  H01L23/00

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.

Abstract translation: 封装包括半导体芯片。 半导体芯片包括测试焊盘和多个微型块焊盘，其中多个微型块焊盘中的每个微型焊盘电连接到测试焊盘。 所述封装还包括衬底; 以及多个微胶片，其被配置为将所述半导体芯片电连接到所述基板，其中所述多个微胶片中的每个微小块电连接到所述多个微型块衬垫中的对应的微型块体。 封装还包括封装衬底，其中封装衬底包括凸块焊盘，其中凸块焊盘的面积大于测试焊盘和多个微型块焊盘的组合面积。 所述封装还包括凸起，所述凸起被配置为将所述衬底电连接到所述封装衬底。

公开(公告)号：US09281056B2

公开(公告)日：2016-03-08

申请号：US14308065

申请日：2014-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Ping-Wei Wang

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/4063 ,  G11C11/409

CPC classification number: G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/412

Abstract: A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors.

Abstract translation: 一种包括位单元的静态随机存取存储器（SRAM），其中所述位单元包括至少两个p型通道门。 SRAM还包括连接到位单元的位线和连接到位单元的位线条。 SRAM还包括连接到位线和位线条的预放电电路，其中预放电电路包括至少两个n型晶体管。 SRAM还包括连接到位线和位线条的交叉耦合晶体管，其中交叉耦合晶体管的每个晶体管是n型晶体管。 SRAM还包括连接到位线和位线条的写入多路复用器，其中写入多路复用器包括两个p型晶体管。

公开(公告)号：US20150380324A1

公开(公告)日：2015-12-31

申请号：US14846605

申请日：2015-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/66 ,  H01L23/58 ,  H01L23/522 ,  H01L23/498

CPC classification number: H01L22/32 ,  G01R1/07378 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/30 ,  H01L22/34 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/585 ,  H01L2221/68331 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05124 ,  H01L2224/05147

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract translation: 本公开的实施例是包括插入器的结构。 插入器具有沿着插入件的周边延伸的测试结构，并且测试结构的至少一部分处于第一再分配元件中。 第一再分配元件位于中介层的衬底的第一表面上。 测试结构是中间的并且电耦合到至少两个探针焊盘。

公开(公告)号：US20150143324A1

公开(公告)日：2015-05-21

申请号：US14084813

申请日：2013-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Yu Wang ,  Wei-Cheng Wu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13005 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.

Abstract translation: 公开了半导体器件设计方法和导电凸块图案增强方法。 在一些实施例中，设计半导体器件的方法包括设计导电凸块图案设计，以及在导电凸块图案设计上实现导电凸块图案增强算法以创建增强的导电凸块图案设计。 基于增强的导电凸块图案设计设计布线图案。 在路由模式上执行设计规则检查（DRC）过程。

公开(公告)号：US20240373626A1

公开(公告)日：2024-11-07

申请号：US18776349

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC: H10B20/00 ,  H01L21/28 ,  H01L21/762 ,  H01L21/765 ,  H01L23/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H10B41/35 ,  H10B41/43 ,  H10B41/49

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US12107001B2

公开(公告)日：2024-10-01

申请号：US18366274

申请日：2023-08-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Harry-Hak-Lay Chuang ,  Chung-Jen Huang ,  Wen-Tuo Huang ,  Wei-Cheng Wu

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/76229 ,  H01L21/02172 ,  H01L21/308 ,  H01L21/76283 ,  H01L21/768 ,  H01L21/76898

Abstract: A semiconductor feature includes: a semiconductor substrate; a dielectric structure and a semiconductor device disposed on the semiconductor substrate; an interconnecting structure disposed in the dielectric structure and connected to the semiconductor device; an STI structure disposed in the semiconductor substrate and surrounding the semiconductor device; two DTI structures penetrating the semiconductor substrate and the STI structure and surrounding the semiconductor device; a passivation structure connected to the semiconductor substrate and the DTI structures and located opposite to the interconnecting structure; and a conductive structure surrounded by the passivation structure, penetrating the semiconductor substrate and the STI structure into the dielectric structure, located between the DTI structures and electrically connected to the semiconductor device via the interconnecting structure.

公开(公告)号：US20240128218A1

公开(公告)日：2024-04-18

申请号：US18156414

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Ming-Shih Yeh ,  An-Jhih Su ,  Der-Chyang Yeh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/3171 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/24 ,  H01L2224/02233 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/06132 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/16147 ,  H01L2224/24146

Abstract: A semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. The first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. The array of conductive bumps is disposed on the array of first pads respectively. The second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. The spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.

公开(公告)号：US20240071911A1

公开(公告)日：2024-02-29

申请号：US18162071

申请日：2023-01-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Haklay Chuang ,  Wen-Tuo Huang ,  Li-Feng Teng ,  Wei-Cheng Wu ,  Yu-Jen Wang

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2225/06524 ,  H01L2225/06527

Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.

公开(公告)号：US20240063030A1

公开(公告)日：2024-02-22

申请号：US17889381

申请日：2022-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Pin Chang ,  Han-Yi Lu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/768

CPC classification number: H01L21/4857 ,  H01L23/49816 ,  H01L23/538 ,  H01L23/562 ,  H01L23/3171 ,  H01L23/49503 ,  H01L21/76871

Abstract: Provided is a semiconductor device including a substrate, an interconnect structure, a first passivation layer, a stress buffer layer, a pad structure, and a second passivation layer. The interconnect structure is disposed on the substrate. The first passivation layer and the stress buffer layer are disposed on the interconnect structure. The pad structure includes: a lower portion embedded in the first passivation layer and the stress buffer layer, and laterally wrapped by the first passivation layer and the stress buffer layer; and an upper portion on the lower portion. The upper portion has a periphery laterally offset outward from a periphery of the lower portion, so that a bottom surface of the upper portion contacts a top surface of the stress buffer layer. The second passivation layer is disposed on the stress buffer layer and laterally wraps the upper portion of the upper portion of the pad structure.