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    SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS
    1.
    发明申请
    SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS 审中-公开

    公开(公告)号：US20190102506A1

    公开(公告)日：2019-04-04

    申请号：US15719743

    申请日：2017-09-29

    申请人： International Business Machines Corporation

    发明人： Anson J. Call ,  Francesco Preda ,  Paul R. Walling

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5077 ,  G06F2217/16 ,  G06F2217/38 ,  G06F2217/40

    摘要： Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

    Modeling localized temperature changes on an integrated circuit chip using thermal potential theory
    3.
    发明授权
    Modeling localized temperature changes on an integrated circuit chip using thermal potential theory 有权
    使用热势理论建模集成电路芯片上的局部温度变化

    公开(公告)号：US09582621B2

    公开(公告)日：2017-02-28

    申请号：US14748595

    申请日：2015-06-24

    申请人： GLOBALFOUNDRIES INC.

    发明人： Frederick G. Anderson ,  Nicholas T. Schmidt

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/38 ,  G06F2217/80 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16152

    摘要： A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.

    摘要翻译： 考虑到从芯片背面的低效散热，模拟了由于与其他装置的自热和热耦合而导致的集成电路芯片上的器件的温度变化。 为了执行这种建模，必须使用测试集成电路（IC）芯片来预定假想热量与IC芯片上不同位置的实际热量的比率。 在测试期间，选择在测试IC芯片上的一个特定位置处的一个测试装置用作热源，而在测试IC芯片上的其他位置处的至少两个其它测试装置用作温度传感器。 热源被偏压，确定了热源和传感器处的温度变化。 这些变化用于计算与特定位置相关联的假热量与实际热量比的值。

    Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs
    5.
    发明授权
    Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs 有权
    用于背面注释和可视化电子设计寄生模型的方法，系统和制造

    公开(公告)号：US09286421B1

    公开(公告)日：2016-03-15

    申请号：US14503408

    申请日：2014-10-01

    申请人： Cadence Design Systems, Inc.

    发明人： Taranjit Singh Kukal ,  Steven Durrill ,  Utpal Bhattacharyya ,  Amit Sharma

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

    摘要： Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.

    摘要翻译： 各种实施例通过在表示中插入复杂模型实例并将模型实例与一个或多个互连模型互连来自动地反向注释电子设计表示。 第一表示中的端口的标识可以在第二表示中与相应端口的标识相关联或更新。 注释第一表示还可以包括将来自第二表示的寄生信息与第一表示相关联或拼接。 将模型用于通过将具有矢量网标识的向量网分成多个具有其自身标量网识别的标量网段来表示向量网。 一些方面自动生成一个显示，用于使用复杂模型注释电子设计的结果可视化。 这些方面中的一些可以进一步包括显示器中的寄生信息和分析结果。

    Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics
    6.
    发明授权
    Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics 有权
    用于分析多结构电子设计的方法，系统和制品，并展示多结构电子设计的分析结果，跨多个设计织物跨越并显示模拟结果

    公开(公告)号：US09280621B1

    公开(公告)日：2016-03-08

    申请号：US14503407

    申请日：2014-10-01

    申请人： Cadence Design Systems, Inc.

    发明人： Arnold Ginetti ,  Vikas Kohli ,  Taranjit Singh Kukal

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

    摘要： Disclosed are techniques to analyze multi-fabric designs. These techniques generate a cross-fabric analysis model by at least identifying first design data in a first design fabric of a multi-fabric electronic design using a first session of a first electronic design automation (EDA) tool, update the cross-fabric simulation model by at least identifying second design data in a second design fabric using a second session of a second EDA tool, and determine analysis results for the multi-fabric electronic design using at least the cross-fabric simulation model. Analysis results may be determined using parasitic, electrical, or performance information. Various EDA tools access their respective native design data in their respective domains or design fabrics and have no access to or visibility of non-native design data while these techniques automatically cross the boundaries between multiple design fabrics to accomplish the tasks of analyzing multi-fabric electronic designs or displaying analysis results therefor.

    摘要翻译： 公开了分析多织物设计的技术。 这些技术通过使用第一电子设计自动化（EDA）工具的第一会话至少识别多结构电子设计的第一设计结构中的第一设计数据来生成交叉结构分析模型，更新交织架模拟模型 通过使用第二EDA工具的第二会话至少识别第二设计结构中的第二设计数据，并使用至少交叉结构仿真模型确定多结构电子设计的分析结果。 可以使用寄生，电气或性能信息来确定分析结果。 各种EDA工具在其各自的领域或设计结构中访问其各自的本机设计数据，并且无法访问或了解非本地设计数据，而这些技术自动跨越多个设计结构之间的边界，从而完成分析多结构电子 设计或展示分析结果。

    DYNAMIC OPTIMIZATION OF DETAILED FLAT DESIGN BASED ON DESIRED FINAL STRUCTURAL ATTRIBUTES
    7.
    发明申请
    DYNAMIC OPTIMIZATION OF DETAILED FLAT DESIGN BASED ON DESIRED FINAL STRUCTURAL ATTRIBUTES 有权
    基于所需最终结构属性的详细平面设计的动态优化

    公开(公告)号：US20150317411A1

    公开(公告)日：2015-11-05

    申请号：US14269543

    申请日：2014-05-05

    申请人： Xerox Corporation

    发明人： Michael R. Furst ,  Charles Donahue Rizzolo ,  William J. Hannaway ,  Stephen C. Morgana ,  Reiner Eschbach

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  B65D5/0254 ,  G06F2217/38

    摘要： A method and system for creating a customized package design. Package design and preference information related to a shape of the package design is received. The preference information includes user-specified information related to one or more levels of one or more structural attributes of the package design. A detailed design is generated that incorporates the user-specified information and a detailed design file is generated and output. Generation of the detailed design includes identifying functional elements associated with the package that correspond to the user-specified information and altering at least one physical characteristic of the identified functional elements based upon the preference information, and incorporating the altered physical characteristic into the detailed design. A determination can be made as to whether the altered detailed design satisfies any constraints associated with the package being design, and the detailed design file can be updated accordingly.

    摘要翻译： 一种用于创建定制包装设计的方法和系统。 接收与包装设计形状相关的包装设计和偏好信息。 偏好信息包括与包装设计的一个或多个结构属性的一个或多个级别相关的用户指定的信息。 生成详细的设计，其中包含用户指定的信息，并生成并输出详细的设计文件。 详细设计的生成包括识别与包装相关联的功能元件，其对应于用户指定的信息，并且基于偏好信息来改变所识别的功能元件的至少一个物理特性，并将改变的物理特征结合到详细设计中。 可以确定改变的详细设计是否满足与正在设计的包相关联的任何限制，并且可以相应地更新详细的设计文件。

    Layout method for printed circuit board
    8.
    发明授权
    Layout method for printed circuit board 有权
    印刷电路板布局方法

    公开(公告)号：US09158880B2

    公开(公告)日：2015-10-13

    申请号：US14043197

    申请日：2013-10-01

    申请人： MediaTek Inc.

    发明人： Fu-Kang Pan ,  Nan-Cheng Chen ,  Shih-Chieh Lin ,  Hui-Chi Tang ,  Ying Liu ,  Yang Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/38 ,  G06F2217/40

    摘要： A layout method for a printed circuit board (PCB) is provided. A memory type of a dynamic random access memory (DRAM) to be mounted on the PCB is obtained. A module group is obtained from a database according to the memory type of the DRAM, wherein the module group includes a plurality of routing modules. A plurality of PCB parameters are obtained. A specific routing module is selected from the module group according to the PCB parameters. The specific routing module is implemented into a layout design of the PCB. The specific routing module includes layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

    摘要翻译： 提供了印刷电路板（PCB）的布局方法。 获得要安装在PCB上的动态随机存取存储器（DRAM）的存储器类型。 根据DRAM的存储器类型从数据库获得模块组，其中模块组包括多个路由模块。 获得多个PCB参数。 根据PCB参数从模块组中选择一个特定的路由模块。 具体的路由模块被实现为PCB的布局设计。 特定路由模块包括关于主芯片，存储芯片以及主芯片和存储芯片之间的路由配置的布局信息。