- 专利标题: Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs
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申请号: US15069881申请日: 2016-03-14
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公开(公告)号: US09449130B1公开(公告)日: 2016-09-20
- 发明人: Taranjit Singh Kukal , Steven Durrill , Utpal Bhattacharyya , Amit Sharma
- 申请人: Cadence Design Systems, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Vista IP Law Group, LLP
- 主分类号: G06F9/455
- IPC分类号: G06F9/455 ; G06F17/50
摘要:
Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.
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