公开(公告)号：US12212315B1

公开(公告)日：2025-01-28

申请号：US18093281

申请日：2023-01-04

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar

IPC: G11C5/14 ,  H03K3/011 ,  H03K17/687 ,  G11C11/4093

Abstract: Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

公开(公告)号：US12184286B1

公开(公告)日：2024-12-31

申请号：US17831685

申请日：2022-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Prakash Kumar Lenka ,  Hari Anand Ravi ,  Jitendra Kumar Yadav

IPC: H03K5/00 ,  G01R29/02 ,  H03K3/017 ,  H03K5/24

Abstract: The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

公开(公告)号：US12182613B1

公开(公告)日：2024-12-31

申请号：US17245506

申请日：2021-04-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Chandra Prakash Manglani ,  Amit Khurana ,  Sunil Prasad Todi

IPC: G06F30/31 ,  G06F3/06 ,  G06F9/48

Abstract: A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file in the first order by executing a second process in parallel to the first process.

公开(公告)号：US12182485B1

公开(公告)日：2024-12-31

申请号：US16209885

申请日：2018-12-04

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Christopher Coffman ,  Hitesh Gannu

IPC: G06F30/33 ,  G06F9/455 ,  G06F30/331 ,  G06F30/3323 ,  G06F30/398 ,  G06F115/02 ,  G06F117/08

Abstract: A shared memory is provided between simulation processors and emulation processors within an emulation chip. The shared memory is configured to enable the simulation processors and the emulation processors to exchange simulation data and emulation data respectively with each other during simulation and emulation operations. The simulation processors and the emulation processors may update their respective simulation and emulation operations in response to the simulation data and the emulation data exchanged via the shared memory.

公开(公告)号：US12141233B1

公开(公告)日：2024-11-12

申请号：US16587790

申请日：2019-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Marco Tony Lloyd Kassis ,  Mina Adel Aziz Farhan ,  Joel Reuben Phillips

IPC: G06F18/214 ,  G06F17/12 ,  G06F17/14 ,  G06N20/00

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.

公开(公告)号：US12099791B1

公开(公告)日：2024-09-24

申请号：US17490496

申请日：2021-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Shadi Saba ,  Roque Alejandro Arcudia Hernandez ,  Uyen Huynh Ha Nguyen ,  Pedro Eugênio Rocha Medeiros ,  Claire Liyan Ying ,  Ruozhi Zhang ,  Gustavo Emanuel Faria Araujo

IPC: G06F30/333

CPC classification number: G06F30/333

Abstract: An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test sequences.

公开(公告)号：US12086529B1

公开(公告)日：2024-09-10

申请号：US17691974

申请日：2022-03-10

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Eric K. Anderson ,  Yang Gao

IPC: G06F30/398 ,  G06F30/3315 ,  G06F119/02

CPC classification number: G06F30/398 ,  G06F30/3315 ,  G06F2119/02

Abstract: Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.

公开(公告)号：US20240296269A1

公开(公告)日：2024-09-05

申请号：US18178463

申请日：2023-03-03

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Bhoumik Shah ,  Jennifer Lee

IPC: G06F30/3308

CPC classification number: G06F30/3308

Abstract: The systems and methods described herein include emulators that implement wrappers comprising instrumentation logic for the emulator components (e.g., memories) to perform certain memory-related functions. These functions allow the physical binary memories of the emulator to behave as a ternary memory. The memory wrappers include instrumentation logic around logic of the physical binary memories. In some cases, embodiments generate the wrappers for the user memory, rather than performing conventional synthesis functions for user-design memories. The inputs include the user ternary RTL, as well as additional potential inputs for pre-compiler control. The wrappers instantiate the operations, such as MPRs or MPWs, and create the ternary-memory support logic to, for example, prevent unknown-value writes and to output unknown values X for unknown-value reads.

公开(公告)号：US11983538B2

公开(公告)日：2024-05-14

申请号：US17659569

申请日：2022-04-18

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Ajay A. Ingle

IPC: G06F9/38 ,  G06F12/0855

CPC classification number: G06F9/3834 ,  G06F12/0855

Abstract: Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In some embodiments, executing load/store instructions in parallel with fills, probes, and store-updates, using separate but identical tag memory arrays, may advantageously improve performance.

公开(公告)号：US11947887B1

公开(公告)日：2024-04-02

申请号：US17953618

申请日：2022-09-27

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Brian Foutz ,  Prateek Kumar Rai ,  Sarthak Singhal ,  Christos Papameletis ,  Vivek Chickermane

IPC: G06F30/333 ,  G06F30/327 ,  G01R31/3185

CPC classification number: G06F30/333 ,  G06F30/327 ,  G01R31/318583

Abstract: A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.