公开(公告)号：US11947887B1

公开(公告)日：2024-04-02

申请号：US17953618

申请日：2022-09-27

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Brian Foutz ,  Prateek Kumar Rai ,  Sarthak Singhal ,  Christos Papameletis ,  Vivek Chickermane

IPC: G06F30/333 ,  G06F30/327 ,  G01R31/3185

CPC classification number: G06F30/333 ,  G06F30/327 ,  G01R31/318583

Abstract: A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

公开(公告)号：US08904256B1

公开(公告)日：2014-12-02

申请号：US13673522

申请日：2012-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Vivek Chickermane ,  Dale Meehl

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/318547

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract translation: 公开了一种使用非常针脚限制的测试装置将压缩测试图案应用于用于半导体制造测试中的芯片设计的方法和装置。 压缩电路插入到电路设计中，压缩信号被操纵以通过串行接口进行通信。 在测试装置上，可以运行ATPG，假设为并行测试接口，导致测试模式可能被压缩为并行格式，然后转换为串行信号。 在芯片上，串行信号并行化，解压缩，然后移入扫描链。 插入的控制器产生时钟和各种控制信号。 可以在测试过程中生成和应用ATPG的常规测试模式，而无需修改ATPG程序节省时间和资源。 还支持使用多个内核构建的集成电路的分层测试，每个核心都具有自己的嵌入式压缩逻辑。

公开(公告)号：US08650524B1

公开(公告)日：2014-02-11

申请号：US13673579

申请日：2012-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Vivek Chickermane ,  Dale Meehl

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/14

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

公开(公告)号：US10996270B1

公开(公告)日：2021-05-04

申请号：US16128177

申请日：2018-09-11

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sameer Chillarige ,  Joe Swenton ,  Anil Malik ,  Krishna Chakravadhanula

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/00 ,  G06F16/28 ,  G01R31/3183

Abstract: Systems and methods for multiple device diagnostics are disclosed herein. Exemplary embodiments provide for a multiple device diagnostic system having a plurality of electronic devices selected for diagnosis based on at least one selection criterion, a diagnosis engine in data communication with a failure database, and a diagnosis results database in data communication with the diagnosis engine. Embodiments further provide that the failure database contains grouped failure data from at least one previously diagnosed electronic device, that the wherein the processor diagnoses defects in one or more of the plurality of electronic devices using the grouped failure data, and that the processor outputs the diagnosis results to the diagnosis results database.

公开(公告)号：US09170301B1

公开(公告)日：2015-10-27

申请号：US13772245

申请日：2013-02-20

Applicant: Cadence Design Systems, Inc.

Inventor： Patrick Gallagher ,  Krishna Chakravadhanula ,  Rajesh Khurana

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3177

CPC classification number: G01R31/31813 ,  G01R31/3177 ,  G01R31/318544 ,  G01R31/318575

Abstract: A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the compacted test patterns in turn. This is repeated for each test pattern to create a set of compacted test patterns conforming to the requirements of the criteria. This method and apparatus provides for fine grained control of low power constraints when testing integrated circuits, and includes benefits such as preventing damage during test from burnout and hot spots, and avoiding failures due to IR drop.

Abstract translation: 公开了一种用于在测试期间应用于集成电路的测试图案的分层压缩的方法和装置。 这些实施例应用分级策略来分类用于压实的测试模式。 针对压实测试模式的一系列标准考虑了测试模式。 在满足所有标准的情况下，测试图案被合并到压实的测试图案中。 如果不满足标准，则依次对每个压实的测试模式考虑测试模式。 对于每个测试图案重复这一点，以创建符合标准要求的一组压实测试图案。 该方法和装置在测试集成电路时提供对低功率约束的细粒度控制，并且包括诸如防止在烧坏和热点期间的测试期间的损坏以及避免由于IR下降引起的故障的益处。