公开(公告)号：US11379644B1

公开(公告)日：2022-07-05

申请号：US17064406

申请日：2020-10-06

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Divyank Mittal ,  Sagar Kumar ,  Vivek Chickermane

IPC: G06F30/333 ,  G06Q50/18 ,  G06F30/31 ,  G06F16/903 ,  G06Q10/06 ,  G06F115/08

Abstract: An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

公开(公告)号：US09606179B1

公开(公告)日：2017-03-28

申请号：US14754351

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Paul Alexander Cunningham ,  Steev Wilcox ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula ,  Brian Edward Foutz

IPC: G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/319 ,  G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/318335 ,  G01R31/318536 ,  G01R31/318547 ,  G01R31/318558 ,  G01R31/31921

Abstract: Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.

公开(公告)号：US09470756B1

公开(公告)日：2016-10-18

申请号：US14738765

申请日：2015-06-12

Applicant: Cadence Design Systems, Inc.

Inventor： Steev Wilcox ,  Brian Edward Foutz ,  Krishna Vijaya Chakravadhanula ,  Vivek Chickermane ,  Paul Alexander Cunningham

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/318563 ,  G01R31/318547 ,  G01R31/318583

Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

Abstract translation: 用于在“测试设计”（DFT）应用中解压缩一组扫描输入数据的方法，系统和集成电路，其中实现可以包括从自动测试设备（ATE）确定应用电路的扫描输入的数量。 基于扫描输入的数量，实现的另一方面可以涉及在集成电路（IC）上生成二维网格。 另一个实现方面可以包括根据依次分布的解压缩逻辑从ATE解压缩扫描输入，使得网格可以在本地应用解压缩逻辑的最后阶段。 根据该方法的方面，IC解压缩逻辑的物理结构对于各个扫描链更易于访问，并减少IC上的拥塞。

公开(公告)号：US08595681B1

公开(公告)日：2013-11-26

申请号：US13717419

申请日：2012-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Senthil Arasu Thirunavukarasu ,  Shaleen Bhabu ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/318533

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

公开(公告)号：US11947887B1

公开(公告)日：2024-04-02

申请号：US17953618

申请日：2022-09-27

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Brian Foutz ,  Prateek Kumar Rai ,  Sarthak Singhal ,  Christos Papameletis ,  Vivek Chickermane

IPC: G06F30/333 ,  G06F30/327 ,  G01R31/3185

CPC classification number: G06F30/333 ,  G06F30/327 ,  G01R31/318583

Abstract: A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

公开(公告)号：US10234504B1

公开(公告)日：2019-03-19

申请号：US15452526

申请日：2017-03-07

Applicant: Cadence Design Systems, Inc.

Inventor： Subhasish Mukherjee ,  Jagjot Kaur ,  Vivek Chickermane ,  Susan Marie Genova

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.

公开(公告)号：US09817069B1

公开(公告)日：2017-11-14

申请号：US14754403

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Steev Wilcox ,  Krishna Vijaya Chakravadhanula ,  Vivek Chickermane ,  Paul Alexander Cunningham ,  Brian Edward Foutz

IPC: G01R31/3177 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/31813 ,  G01R31/318335 ,  G01R31/318385 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31921

Abstract: Systems and methods for a sequential decompressor which builds equations predictably provide a first-in, first out (“FIFO”) shift register which is fed by a first XOR decompressor and provides outputs to a second XOR decompressor.

公开(公告)号：US09702934B1

公开(公告)日：2017-07-11

申请号：US14921769

申请日：2015-10-23

Applicant: Cadence Design Systems, Inc.

Inventor： Dale Edward Meehl ,  Vivek Chickermane

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3183 ,  G01R31/3177

CPC classification number: G01R31/318335 ,  G01R31/3177 ,  G01R31/318547

Abstract: Systems and methods disclosed herein provide for efficiently loading mask data to the mask register bits from the decompression network outputs of an ATPG system. The systems and methods also provide an elastic interface utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the number of input variables utilized during the loading of the mask data to the mask register bits.

公开(公告)号：US09470755B1

公开(公告)日：2016-10-18

申请号：US14738746

申请日：2015-06-12

Applicant: Cadence Design Systems, Inc.

Inventor： Brian Edward Foutz ,  Steev Wilcox ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula ,  Paul Alexander Cunningham

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3177

CPC classification number: G06F17/5077 ,  G01R31/318335 ,  G01R31/318558 ,  G01R31/318583

Abstract: Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.

Abstract translation: 用于实现集成电路设计的物理高效扫描的方法和计算机可读介质可以包括选择二维网格尺寸以暴露于该方法，二维网格具有包括第一侧长度，第二边长度， 和一些翻牌。 执行该方法以选择使压缩效率最大化并限制IC上的布线拥塞的二维网格尺寸。 一方面，可以在网格的每个区域上执行该方法，该区域维持相应的第一边长和相应的第二边长大于1的区域，包括选择较大边，确定较大边是奇数还是偶数， 并且将较大侧的网格划分成每个具有翻牌比例的两个区域。 所得区域的扫描是有效的，因此有助于集成电路设计和随后的制造。

公开(公告)号：US10775435B1

公开(公告)日：2020-09-15

申请号：US16177621

申请日：2018-11-01

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Christos Papameletis ,  Brian Edward Foutz ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

IPC: G01R31/3185

Abstract: Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).