公开(公告)号：US12055586B1

公开(公告)日：2024-08-06

申请号：US18113898

申请日：2023-02-24

Applicant: Cadence Design Systems, Inc.

Inventor： Sagar Kumar ,  Rajesh Khurana ,  Vivek Chickermane

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31723 ,  G01R31/318555 ,  G01R31/318597

Abstract: Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.

公开(公告)号：US09633163B1

公开(公告)日：2017-04-25

申请号：US14589537

申请日：2015-01-05

Applicant: Cadence Design Systems, Inc.

Inventor： Hitesh Mohan Kumar ,  Sagar Kumar ,  Ankur Gupta

IPC: G06F17/50 ,  H01L23/498 ,  H01L27/02 ,  H01L21/66 ,  G06F9/44 ,  G06F17/30

CPC classification number: G06F17/5077 ,  G06F8/71 ,  G06F17/30867 ,  G06F17/5045 ,  G06F17/5081 ,  G06F17/509 ,  G06F2217/06 ,  H01L22/34 ,  H01L23/49838 ,  H01L27/0207

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more processors, an electronic design and visually displaying a plurality of possible route sets associated with the electronic design at a graphical user interface. The method may include providing an option to select between the plurality of possible route sets at the graphical user interface.

公开(公告)号：US11379644B1

公开(公告)日：2022-07-05

申请号：US17064406

申请日：2020-10-06

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Divyank Mittal ,  Sagar Kumar ,  Vivek Chickermane

IPC: G06F30/333 ,  G06Q50/18 ,  G06F30/31 ,  G06F16/903 ,  G06Q10/06 ,  G06F115/08

Abstract: An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

公开(公告)号：US10289788B1

公开(公告)日：2019-05-14

申请号：US14954033

申请日：2015-11-30

Applicant: Cadence Design Systems, Inc.

Inventor： Hitesh Mohan Kumar ,  Matthew Timothy Bromley ,  Vikas Kohli ,  Sagar Kumar

IPC: G06F17/50 ,  G06F16/22 ,  G06F16/28

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.