公开(公告)号：US11379644B1

公开(公告)日：2022-07-05

申请号：US17064406

申请日：2020-10-06

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Divyank Mittal ,  Sagar Kumar ,  Vivek Chickermane

IPC: G06F30/333 ,  G06Q50/18 ,  G06F30/31 ,  G06F16/903 ,  G06Q10/06 ,  G06F115/08

Abstract: An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.

公开(公告)号：US10528689B1

公开(公告)日：2020-01-07

申请号：US15364049

申请日：2016-11-29

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Vivek Chickermane ,  Dhruv Dua ,  Krishna Vijaya Chakravadhanula

IPC: G06F17/50

Abstract: A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least one of verifying structural descriptions of the integrated circuit in the ICL files and verifying an ability to use chip level inputs to access instruments in the integrated circuit. The verification procedure is performed prior to a simulation in which a migrated test pattern is applied to the integrated circuit.

公开(公告)号：US12055586B1

公开(公告)日：2024-08-06

申请号：US18113898

申请日：2023-02-24

Applicant: Cadence Design Systems, Inc.

Inventor： Sagar Kumar ,  Rajesh Khurana ,  Vivek Chickermane

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31723 ,  G01R31/318555 ,  G01R31/318597

Abstract: Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.

公开(公告)号：US10796041B1

公开(公告)日：2020-10-06

申请号：US16389733

申请日：2019-04-19

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Vivek Chickermane ,  Divyank Mittal ,  Balveer Singh Koranga

IPC: G06F30/30 ,  G01R31/3185

Abstract: Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.

公开(公告)号：US09170301B1

公开(公告)日：2015-10-27

申请号：US13772245

申请日：2013-02-20

Applicant: Cadence Design Systems, Inc.

Inventor： Patrick Gallagher ,  Krishna Chakravadhanula ,  Rajesh Khurana

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3177

CPC classification number: G01R31/31813 ,  G01R31/3177 ,  G01R31/318544 ,  G01R31/318575

Abstract: A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the compacted test patterns in turn. This is repeated for each test pattern to create a set of compacted test patterns conforming to the requirements of the criteria. This method and apparatus provides for fine grained control of low power constraints when testing integrated circuits, and includes benefits such as preventing damage during test from burnout and hot spots, and avoiding failures due to IR drop.

Abstract translation: 公开了一种用于在测试期间应用于集成电路的测试图案的分层压缩的方法和装置。 这些实施例应用分级策略来分类用于压实的测试模式。 针对压实测试模式的一系列标准考虑了测试模式。 在满足所有标准的情况下，测试图案被合并到压实的测试图案中。 如果不满足标准，则依次对每个压实的测试模式考虑测试模式。 对于每个测试图案重复这一点，以创建符合标准要求的一组压实测试图案。 该方法和装置在测试集成电路时提供对低功率约束的细粒度控制，并且包括诸如防止在烧坏和热点期间的测试期间的损坏以及避免由于IR下降引起的故障的益处。