公开(公告)号：US12086529B1

公开(公告)日：2024-09-10

申请号：US17691974

申请日：2022-03-10

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Eric K. Anderson ,  Yang Gao

IPC: G06F30/398 ,  G06F30/3315 ,  G06F119/02

CPC classification number: G06F30/398 ,  G06F30/3315 ,  G06F2119/02

Abstract: Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.