公开(公告)号：US20180261162A1

公开(公告)日：2018-09-13

申请号：US15979658

申请日：2018-05-15

申请人： Ignis Innovation Inc.

发明人： Javid Jaffari ,  Gholamreza Chaji ,  Tong Liu

IPC分类号： G09G3/3258 ,  G09G3/3233 ,  G09G3/3291 ,  G06F17/50

CPC分类号： G09G3/3258 ,  G06F17/5018 ,  G06F2217/80 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2310/0289 ,  G09G2320/0233 ,  G09G2320/0271 ,  G09G2320/029 ,  G09G2320/041 ,  G09G2320/0626 ,  G09G2320/0693

摘要： Disclosed is a circuit and technique to determine the temperature of an AMOLED display in order to calibrate programming data signals. The temperature of selected pixels of a plurality of pixels in an AMOLED display is measured via one of several disclosed methods. A thermal sensor for the selected pixels may be used. A measurement of output voltage data may be used to estimate temperature. A finite element analysis model may be used based on consumed power of the selected pixel. The temperature data for the selected pixel is then interpolated to the neighboring non-selected pixels to estimate the temperature of those pixels.

公开(公告)号：US20180210992A1

公开(公告)日：2018-07-26

申请号：US15792820

申请日：2017-10-25

申请人： International Business Machines Corporation

发明人： Nagashyamala R. Dhanwada ,  Arun Joseph ,  Arya Madhusoodanan ,  Spandana V. Rachamalla

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78 ,  G06F2217/80

摘要： Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.

公开(公告)号：US10020267B2

公开(公告)日：2018-07-10

申请号：US15412535

申请日：2017-01-23

申请人： Altera Corporation

发明人： Arifur Rahman ,  Karthik Chandrasekar

IPC分类号： H01L23/52 ,  H01L23/00 ,  G06F17/50 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/562 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/40 ,  G06F2217/78 ,  G06F2217/80 ,  G06F2217/82 ,  G06F2217/84 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/16 ,  H01L27/0688 ,  H01L2224/16227 ,  H03K19/177

摘要： A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.

公开(公告)号：US10019545B2

公开(公告)日：2018-07-10

申请号：US14304499

申请日：2014-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Min-Chie Jeng ,  Chung-Kai Lin ,  Ke-Wei Su ,  Yi-Shun Huang ,  Ya-Chin Liang ,  Cheng Hsiao ,  Juan Yi Chen ,  Wai-Kit Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068 ,  G06F2217/80

摘要： A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.

公开(公告)号：US10002212B2

公开(公告)日：2018-06-19

申请号：US15377309

申请日：2016-12-13

申请人： International Business Machines Corporation

发明人： Bishop Brock ,  Michael S. Floyd ,  Erika Gunadi ,  Nan Ni ,  Srinivasan Ramani ,  Ken V. Vu

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/78 ,  G06F2217/80

摘要： A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

公开(公告)号：US09959371B2

公开(公告)日：2018-05-01

申请号：US14428122

申请日：2013-03-20

申请人： Tata Consultancy Services Limited

发明人： Amarendra K. Singh ,  Harshad Bhagwat ,  Umesh Singh ,  Rohan Amarnath ,  Anand Sivasubramaniam

IPC分类号： G06F17/50 ,  H05K7/20

CPC分类号： G06F17/5004 ,  G06F17/5072 ,  G06F2217/78 ,  G06F2217/80 ,  H05K7/20836

摘要： A method and system is disclosed for maintaining Power Usage Effectiveness (PUE) of a new data center constant or within narrow range around efficient level during ramping up stage of the data center. The method comprises of capturing a plurality of design and operational parameters of the data center, computing an efficient design for the data center at full occupancy, and maintaining the Power Usage Effectiveness constant or within narrow range around efficient level at a current occupancy during a ramp up period of the data center.

公开(公告)号：US20180101631A1

公开(公告)日：2018-04-12

申请号：US15291034

申请日：2016-10-11

申请人： Ixia

发明人： Michelle Renee Havard

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/3058 ,  G06F2217/78 ,  G06F2217/80

摘要： Methods, systems, and computer readable media for obtaining power consumption data associated with packet processing are disclosed. One method for obtaining power consumption data associated with packet processing occurs at a test device. The method includes sending, via a first communications interface, at least one test packet to a system under test (SUT). The method also includes receiving, via a second communications interface, power consumption data associated with the at least one test packet. The method further includes correlating the power consumption data and test packet information.

公开(公告)号：US20180095932A1

公开(公告)日：2018-04-05

申请号：US15281651

申请日：2016-09-30

申请人： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

发明人： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

IPC分类号： G06F15/82 ,  G06F1/32

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3293 ,  G06F17/5054 ,  G06F2217/78 ,  G06F2217/80

摘要： In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US09934352B2

公开(公告)日：2018-04-03

申请号：US14940218

申请日：2015-11-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chi-Wen Chang ,  Hui Yu Lee ,  Ya Yun Liu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5068 ,  G06F2217/80

摘要： A method of making a three-dimensional (3D) integrated circuit (IC) includes performing a series of simulations of operations of a first die of the 3DIC in response to a corresponding series of input vectors and at least one environment temperature. The method also includes adjusting, for at least one simulation in the series of simulations, the at least one environment temperature based on an operational temperature profile of a second die of the 3DIC.

公开(公告)号：US09881120B1

公开(公告)日：2018-01-30

申请号：US14871735

申请日：2015-09-30

申请人： Cadence Design Systems, Inc.

发明人： Arnold Ginetti ,  Steven Durrill ,  Taranjit Singh Kukal

IPC分类号： G06F17/50 ,  G06F7/76 ,  G06F1/26 ,  G06F15/78

CPC分类号： G06F17/5081 ,  G06F1/266 ,  G06F7/76 ,  G06F15/7867 ,  G06F17/5018 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5063 ,  G06F2217/80 ,  H01L23/50 ,  H05K1/0203 ,  H05K3/0005

摘要： Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.