公开(公告)号：US12029123B2

公开(公告)日：2024-07-02

申请号：US17237607

申请日：2021-04-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Hao Chen ,  Hui Yu Lee ,  Jui-Feng Kuan

IPC分类号： H10N10/17 ,  H01L23/38 ,  H01L25/16 ,  H10N10/01 ,  H10N10/80

CPC分类号： H10N10/17 ,  H01L23/38 ,  H01L25/167 ,  H10N10/01 ,  H10N10/80

摘要： A semiconductor structure includes an optical component and a thermal control mechanism adjacent to the optical component and configured to control a temperature of the optical component. The thermal control mechanism includes a conductive structure, a first thermoelectric member and a second thermoelectric member opposite to the first thermoelectric member. The first thermoelectric member and the second thermoelectric member are electrically connected to the conductive structure. The first thermoelectric member and the second thermoelectric member have opposite conductive types. The semiconductor structure further includes a first dielectric layer surrounding the optical component and a portion of the thermal control mechanism, wherein the conductive structure is over the first dielectric layer, and the first thermoelectric member and the second thermoelectric member are surrounded by the first dielectric layer. The semiconductor structure further includes a first via extending through the first dielectric layer and electrically connected to the conductive structure.

公开(公告)号：US10910365B2

公开(公告)日：2021-02-02

申请号：US16569382

申请日：2019-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hui-Yu Lee ,  Chi-Wen Chang ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC分类号： H01L23/34 ,  H01L23/38 ,  H01L27/06 ,  H01L23/00 ,  H01L25/065 ,  H01L35/26 ,  H01L35/18 ,  H01L23/48

摘要： A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

公开(公告)号：US10685161B2

公开(公告)日：2020-06-16

申请号：US16204844

申请日：2018-11-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chi-Wen Chang ,  Jui-Feng Kuan

IPC分类号： G06F17/50 ,  G06F30/392 ,  G06F30/398

摘要： A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.

公开(公告)号：US10095827B2

公开(公告)日：2018-10-09

申请号：US15943428

申请日：2018-04-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chi-Wen Chang ,  Hui Yu Lee ,  Ya Yun Liu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC分类号： G06F9/455 ,  G06F17/50

摘要： A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC). The method further includes identifying a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions. The method further includes manufacturing the semiconductor device.

公开(公告)号：US10540475B2

公开(公告)日：2020-01-21

申请号：US16149572

申请日：2018-10-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chi-Wen Chang ,  Hui Yu Lee ,  Ya Yun Liu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC分类号： G06F9/455 ,  G06F17/50

摘要： A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.

公开(公告)号：US09418200B2

公开(公告)日：2016-08-16

申请号：US14799762

申请日：2015-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ching-Yu Chai ,  Chin-Sheng Chen ,  Wei-Yi Hu ,  Jui-Feng Kuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F17/5072

摘要： A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.

摘要翻译： 一种用于设计集成电路的系统包括至少一个处理器和包括用于一个或多个程序的计算机程序代码的至少一个存储器。 所述至少一个存储器和所述计算机程序代码被配置为与所述至少一个处理器一起使得所述系统从设备阵列设计模块接收所提出的设备阵列布局。 设备阵列设计模块被配置为生成所提出的设备阵列布局，而不受一组系统设计规则限制。 该系统还被修改了包括所提出的器件阵列布局的集成电路的原理图。 进一步导致系统确定修改的原理图是否违反一个或多个系统设计规则约束。

公开(公告)号：US09122833B2

公开(公告)日：2015-09-01

申请号：US14086127

申请日：2013-11-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Ching-Shun Yang ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5036

摘要： A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration. The method further includes generating a layout, wherein the layout does not take the artificial elements into consideration, and performing a post-layout simulation, wherein the post-layout simulation does not take the artificial elements into consideration.

摘要翻译： 设计基于鳍状场效应晶体管（FinFET）的电路的方法包括：使用处理器设计基于性能规格的第一电路原理图设计，第一电路示意图设计不含人造元件，其中使用人造元件 以模拟基于FinFET的电路的电气性能。 该方法还包括使用处理器来修改第一电路原理图设计中的至少一个器件以形成考虑人造元件的第二电路示意图。 该方法还包括使用第二电路原理图执行预布局仿真并考虑人造元件。 该方法还包括生成布局，其中布局不考虑人造元素，并执行后布局模拟，其中后布局模拟不考虑人造元素。

公开(公告)号：US20150179568A1

公开(公告)日：2015-06-25

申请号：US14137679

申请日：2013-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Wen Chang ,  Hui Yu Lee ,  Ya Yun Liu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC分类号： H01L23/522 ,  H01L23/528 ,  G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5072 ,  G06F2217/02 ,  G06F2217/66 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first ILV to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for ECO purpose.

摘要翻译： 一种装置包括第一层和第二层。 第二层高于第一层。 第一层包括第一个单元格。 第二层包括第二单元和第三单元。 第三小区包括将第一层中的第一小区耦合到第二层中的第二小区的第一ILV。 第三单元还包括第二ILV，第一ILV和第二ILV沿第一方向延伸。 第一层还包括第四个单元格。 第二层还包括第五个单元格。 第三单元的第二ILV被布置成将第一层的第四单元与第二层的第五单元连接。 在一些实施例中，第二层还包括备用单元，其包括用于ECO目的的备用ILV。

公开(公告)号：US12055800B2

公开(公告)日：2024-08-06

申请号：US17443668

申请日：2021-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Hao Chen ,  Hui Yu Lee ,  Jui-Feng Kuan ,  Chien-Te Wu

IPC分类号： G02F1/01 ,  H10N10/01 ,  H10N10/17 ,  H10N10/80 ,  H10N10/852 ,  H10N10/855

CPC分类号： G02F1/0147 ,  G02F1/011 ,  H10N10/01 ,  H10N10/17 ,  H10N10/80 ,  G02F2203/50 ,  H10N10/852 ,  H10N10/855

摘要： A semiconductor structure includes, an optical component and a thermal control mechanism. The optical component includes a first main path that splits into a first side path and a second side path so that the first side path and the second side path are separated from one another. The thermal control mechanism configured to control a temperature of both the first side path and the second side path, wherein the first thermal control mechanism includes a first thermoelectric member and a second thermoelectric member that are positioned between the first side path and the second side path and the first thermoelectric member and the second thermoelectric member have opposite conductive types.

公开(公告)号：US11852967B2

公开(公告)日：2023-12-26

申请号：US17209701

申请日：2021-03-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD

发明人： Yu-Hao Chen ,  Hui-Yu Lee ,  Jui-Feng Kuan ,  Chien-Te Wu

IPC分类号： G03F1/36 ,  G06F30/398

CPC分类号： G03F1/36 ,  G06F30/398

摘要： A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.