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8 条记录 (耗时 0.017 秒)

    Integrated circuit design flow with device array layout generation
    2.
    发明授权
    Integrated circuit design flow with device array layout generation 有权
    集成电路设计流程与设备阵列布局生成

    公开(公告)号：US09092589B2

    公开(公告)日：2015-07-28

    申请号：US14193527

    申请日：2014-02-28

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Ching-Yu Chai ,  Chin-Sheng Chen ,  Wei-Yi Hu ,  Jui-Feng Kuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F17/5072

    摘要： A system for designing an integrated circuit generates a schematic of the integrated circuit based on a set of system design rule constraints. The system also receives a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from the set of system design rule constraints. The system further generates a revised schematic of the integrated circuit including the proposed device array layout. The system additionally determines if the revised schematic violates one or more of the system design rule constraints.

    摘要翻译： 用于设计集成电路的系统基于一组系统设计规则约束产生集成电路的示意图。 该系统还从设备阵列设计模块接收提出的器件阵列布局。 器件阵列设计模块被配置为生成所提出的器件阵列布局，而不受系统设计规则约束的约束。 该系统进一步产生包括所提出的器件阵列布局的集成电路的修改示意图。 该系统另外确定修改后的原理图是否违反了系统设计规则约束中的一个或多个。

    System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information
    4.
    发明授权
    System, method and associated computer readable medium for designing integrated circuit with pre-layout RC information 有权

    公开(公告)号：US10127338B2

    公开(公告)日：2018-11-13

    申请号：US14969647

    申请日：2015-12-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Chin-Sheng Chen ,  Ching-Yu Chai ,  Wei-Yi Hu

    IPC分类号： G06F17/50

    摘要： A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

    Integrated circuit modeling method using resistive capacitance information
    5.
    发明授权
    Integrated circuit modeling method using resistive capacitance information 有权

    公开(公告)号：US09996643B2

    公开(公告)日：2018-06-12

    申请号：US14543352

    申请日：2014-11-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Ching-Shun Yang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/5045 ,  G06F2217/74

    摘要： A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

    Integrated circuit design system and method of generating proposed device array layout
    7.
    发明授权
    Integrated circuit design system and method of generating proposed device array layout 有权
    集成电路设计系统和产生提出的器件阵列布局的方法

    公开(公告)号：US09418200B2

    公开(公告)日：2016-08-16

    申请号：US14799762

    申请日：2015-07-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Ching-Yu Chai ,  Chin-Sheng Chen ,  Wei-Yi Hu ,  Jui-Feng Kuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F17/5072

    摘要： A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.

    摘要翻译： 一种用于设计集成电路的系统包括至少一个处理器和包括用于一个或多个程序的计算机程序代码的至少一个存储器。 所述至少一个存储器和所述计算机程序代码被配置为与所述至少一个处理器一起使得所述系统从设备阵列设计模块接收所提出的设备阵列布局。 设备阵列设计模块被配置为生成所提出的设备阵列布局，而不受一组系统设计规则限制。 该系统还被修改了包括所提出的器件阵列布局的集成电路的原理图。 进一步导致系统确定修改的原理图是否违反一个或多个系统设计规则约束。

    Method of designing fin field effect transistor (FinFET)-based circuit and system for implementing the same
    8.
    发明授权
    Method of designing fin field effect transistor (FinFET)-based circuit and system for implementing the same 有权
    设计基于鳍状场效应晶体管（FinFET）的电路及其实现方法

    公开(公告)号：US09122833B2

    公开(公告)日：2015-09-01

    申请号：US14086127

    申请日：2013-11-21

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Ching-Shun Yang ,  Yi-Kan Cheng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5036

    摘要： A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration. The method further includes generating a layout, wherein the layout does not take the artificial elements into consideration, and performing a post-layout simulation, wherein the post-layout simulation does not take the artificial elements into consideration.

    摘要翻译： 设计基于鳍状场效应晶体管（FinFET）的电路的方法包括：使用处理器设计基于性能规格的第一电路原理图设计，第一电路示意图设计不含人造元件，其中使用人造元件 以模拟基于FinFET的电路的电气性能。 该方法还包括使用处理器来修改第一电路原理图设计中的至少一个器件以形成考虑人造元件的第二电路示意图。 该方法还包括使用第二电路原理图执行预布局仿真并考虑人造元件。 该方法还包括生成布局，其中布局不考虑人造元素，并执行后布局模拟，其中后布局模拟不考虑人造元素。